Issued Patents All Time
Showing 51–65 of 65 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9146867 | Methods and apparatus to access memory using runtime characteristics | Jeffrey Clifford Mogul, Mehul A. Shah, Eric A. Anderson | 2015-09-29 |
| 9003247 | Remapping data with pointer | Doe Hyun Yoon, Jichuan Chang, Parthasarathy Ranganathan, Norman Paul Jouppi | 2015-04-07 |
| 8990646 | Memory error test routine | Norman Paul Jouppi, Melvin K. Benedict, Andrew C. Walton | 2015-03-24 |
| 8966348 | Memory error identification based on corrupted symbol patterns | Doe Hyun Yoon, Jichuan Chang | 2015-02-24 |
| 8938589 | Interface methods and apparatus for memory devices using arbitration | Norman Paul Jouppi | 2015-01-20 |
| 8892808 | Retention-value associated memory | Jichuan Chang, Parthasarathy Ranganathan | 2014-11-18 |
| 8788904 | Methods and apparatus to perform error detection and correction | Sheng Li, Norman Paul Jouppi | 2014-07-22 |
| 8661298 | Controlling nanostore operation based on monitored performance | Parthasarathy Ranganathan, Jichuan Chang | 2014-02-25 |
| 8639968 | Computing system reliability | Doe Hyun Yoon, Jichuan Chang, Parthasarathy Ranganathan, Norman Paul Jouppi | 2014-01-28 |
| 8638600 | Random-access memory with dynamically adjustable endurance and retention | Jichuan Chang, Parthasarathy Ranganathan | 2014-01-28 |
| 8537634 | Parallelized check pointing using MATs and through silicon VIAs (TSVs) | Norman Paul Jouppi | 2013-09-17 |
| 8516271 | Securing non-volatile memory regions | Paolo Faraboschi, Parthasarathy Ranganathan | 2013-08-20 |
| 8392761 | Memory checkpointing using a co-located processor and service processor | Matteo Monchiero, Partha Ranganathan | 2013-03-05 |
| 8108718 | Checkpointing in massively parallel processing | Norman Paul Jouppi | 2012-01-31 |
| 7478190 | Microarchitectural wire management for performance and power in partitioned architectures | Rajeev Balasubramonian, Liqun Cheng, John L. Carter, Karthik Ramani | 2009-01-13 |