Issued Patents All Time
Showing 1–25 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11442729 | Bit-packed array processing using SIMD | Junwhan Ahn, Andrew McCormick, Yuanwei Fang, Yixin Luo | 2022-09-13 |
| 10817178 | Compressing and compacting memory on a memory device wherein compressed memory pages are organized by size | Sheng Li, Parthasarathy Ranganathan | 2020-10-27 |
| 10691344 | Separate memory controllers to access data in memory | Doe Hyun Yoon, Sheng Li, Ke Chen, Parthasarathy Ranganathan, Norman Paul Jouppi | 2020-06-23 |
| 10585602 | Smart memory buffers | Doe Hyun Yoon, Naveen Muralimanohar, Parthasarathy Ranganathan | 2020-03-10 |
| 10572378 | Dynamic memory expansion by data compression | Sheng Li, Jishen Zhao | 2020-02-25 |
| 10474584 | Storing cache metadata separately from integrated circuit containing cache controller | Justin James Meza, Parthasarathy Ranganathan | 2019-11-12 |
| 10331560 | Cache coherence in multi-compute-engine systems | Sheng Li | 2019-06-25 |
| 10270652 | Network management | Parthasarathy Ranganathan | 2019-04-23 |
| 10152247 | Atomically committing write requests | Sheng Li, Jishen Zhao, Parthasarathy Ranganathan, Alistair Veitch, Kevin T. Lim +1 more | 2018-12-11 |
| 10108239 | Computing devices operable on recovered waste heat | Chandrakant Patel, Cullen E. Bash | 2018-10-23 |
| 10025663 | Local checkpointing using a multi-level cell | Doe Hyun Yoon, Robert Schreiber, Paolo Faraboschi, Naveen Muralimanohar, Parthasarathy Ranganathan | 2018-07-17 |
| 10019176 | Smart memory buffers | Doe Hyun Yoon, Naveen Muralimanohar, Parthasarathy Ranganathan | 2018-07-10 |
| 9934085 | Invoking an error handler to handle an uncorrectable error | Doe Hyun Yoon, Naveen Muralimanohar, Parthasarathy Ranganathan, Robert Schreiber, Norman Paul Jouppi | 2018-04-03 |
| 9846653 | Performing write operations on main memory | Doe Hyun Yoon, Robert Schreiber | 2017-12-19 |
| 9773531 | Accessing memory | Doe Hyun Yoon, Naveen Muralimanohar, Parthasarathy Ranganthan | 2017-09-26 |
| 9767070 | Storage system with a memory blade that generates a computational result for a storage device | Kevin T. Lim, Parthasarathy Ranganathan | 2017-09-19 |
| 9710335 | Versioned memory Implementation | Doe Hyun Yoon, Terence P. Kelly, Naveen Muralimanohar, Robert Schreiber, Parthasarathy Ranganathan | 2017-07-18 |
| 9601189 | Representing data using a group of multilevel memory cells | Doe Hyun Yoon, Naveen Muralimanohar, Robert Schreiber, Norman Paul Jouppi | 2017-03-21 |
| 9575889 | Memory server | Parthasarathy Ranganathan, Kevin T. Lim | 2017-02-21 |
| 9514044 | Multi-level cache tracking table | Doe Hyun Yoon, Parthasarathy Ranganathan | 2016-12-06 |
| 9348527 | Storing data in persistent hybrid memory | Parthasarathy Ranganathan | 2016-05-24 |
| 9176544 | Computer racks | Justin James Meza, Parthasarathy Ranganathan, Amip J. Shah, Cullen E. Bash, Chih-Ching Shih | 2015-11-03 |
| 9128845 | Dynamically partition a volatile memory for a cache and a memory partition | Parthasarathy Ranganathan | 2015-09-08 |
| 9081891 | Reconfigurable crossbar networks | Parthasarathy Ranganathan, Kevin T. Lim | 2015-07-14 |
| 9063864 | Storing data in presistent hybrid memory | Parthasarathy Ranganathan | 2015-06-23 |