Issued Patents All Time
Showing 25 most recent of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417406 | Virtualizing external memory as local to a machine learning accelerator | Lawrence J. Madar, III, Temitayo Fadelu, Harshit Khaitan | 2025-09-16 |
| 12197959 | Preemption in a machine learning hardware accelerator | Temitayo Fadelu, JiHong Min, Dongdong Li, Suyog Gupta, Jason Jong Kyu Park | 2025-01-14 |
| 12079711 | Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies | Uday Kumar Dasari, Olivier Temam, Dong Hyuk Woo | 2024-09-03 |
| 12061968 | Neural network instruction set architecture | Dong Hyuk Woo, Olivier Temam, Harshit Khaitan | 2024-08-13 |
| 12013780 | Multi-partition memory sharing with multiple components | Suyog Gupta, Uday Kumar Dasari, Ali Iranli, Pavan Thirunagari, Vinu Vijay Kumar +1 more | 2024-06-18 |
| 11948060 | Neural network accelerator tile architecture with three-dimensional stacking | Andreas Nowatzyk, Olivier Temam, Uday Kumar Dasari | 2024-04-02 |
| 11816045 | Exploiting input data sparsity in neural network compute units | Dong Hyuk Woo | 2023-11-14 |
| 11816480 | Neural network compute tile | Olivier Temam, Harshit Khaitan, Dong Hyuk Woo | 2023-11-14 |
| 11727259 | Neural network accelerator with parameters resident on chip | Olivier Temam, Harshit Khaitan, Dong Hyuk Woo | 2023-08-15 |
| 11586701 | Low-power adder circuit | Anand Suresh Kane | 2023-02-21 |
| 11501144 | Neural network accelerator with parameters resident on chip | Olivier Temam, Harshit Khaitan, Dong Hyuk Woo | 2022-11-15 |
| 11422801 | Neural network compute tile | Olivier Temam, Harshit Khaitan, Dong Hyuk Woo | 2022-08-23 |
| 11379707 | Neural network instruction set architecture | Dong Hyuk Woo, Olivier Temam, Harshit Khaitan | 2022-07-05 |
| 11366877 | Matrix processing apparatus | Rahul Nagarajan, Dong Hyuk Woo, Christopher Daniel Leary | 2022-06-21 |
| 11176493 | Virtualizing external memory as local to a machine learning accelerator | Lawrence J. Madar, III, Temitayo Fadelu, Harshit Khaitan | 2021-11-16 |
| 11170469 | Image transformation for machine learning | Carrell Daniel Killebrew, Dong Hyuk Woo | 2021-11-09 |
| 11106606 | Exploiting input data sparsity in neural network compute units | Dong Hyuk Woo | 2021-08-31 |
| 11099772 | Hardware double buffering using a special purpose computational unit | Olivier Temam, Harshit Khaitan, Dong Hyuk Woo | 2021-08-24 |
| 10936942 | Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies | Uday Kumar Dasari, Olivier Temam, Dong Hyuk Woo | 2021-03-02 |
| 10885434 | Alternative loop limits for accessing data in multi-dimensional tensors | Olivier Temam, Harshit Khaitan, Dong Hyuk Woo | 2021-01-05 |
| 10824692 | Low-power adder circuit | Anand Suresh Kane | 2020-11-03 |
| 10802956 | Accessing prologue and epilogue data | Olivier Temam, Harshit Khaitan, Dong Hyuk Woo | 2020-10-13 |
| 10719575 | Matrix processing apparatus | Rahul Nagarajan, Dong Hyuk Woo, Christopher Daniel Leary | 2020-07-21 |
| 10534607 | Accessing data in multi-dimensional tensors using adders | Olivier Temam, Harshit Khaitan, Dong Hyuk Woo | 2020-01-14 |
| 10534578 | Multi-input floating-point adder | — | 2020-01-14 |