Issued Patents All Time
Showing 25 most recent of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12339923 | Permuting in a matrix-vector processor | Dong Hyuk Woo, Gregory Michael Thorson, Andrew Everett Phelps, Jonathan Ross, Christopher Aaron Clark | 2025-06-24 |
| 12292473 | Yield improvements for three-dimensionally stacked neural network accelerators | Andreas Nowatzyk | 2025-05-06 |
| 12165048 | Neural network crossbar stack | Pierre-Luc Cantin | 2024-12-10 |
| 12079711 | Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies | Uday Kumar Dasari, Ravi Narayanaswami, Dong Hyuk Woo | 2024-09-03 |
| 12061968 | Neural network instruction set architecture | Ravi Narayanaswami, Dong Hyuk Woo, Harshit Khaitan | 2024-08-13 |
| 11966833 | Accelerating neural networks in hardware using interconnected crossbars | Pierre-Luc Cantin | 2024-04-23 |
| 11948060 | Neural network accelerator tile architecture with three-dimensional stacking | Andreas Nowatzyk, Ravi Narayanaswami, Uday Kumar Dasari | 2024-04-02 |
| 11940946 | Vector reduction processor | Gregory Michael Thorson, Andrew Everett Phelps | 2024-03-26 |
| 11836598 | Yield improvements for three-dimensionally stacked neural network accelerators | Andreas Nowatzyk | 2023-12-05 |
| 11816480 | Neural network compute tile | Ravi Narayanaswami, Harshit Khaitan, Dong Hyuk Woo | 2023-11-14 |
| 11748443 | Permuting in a matrix-vector processor | Dong Hyuk Woo, Gregory Michael Thorson, Andrew Everett Phelps, Jonathan Ross, Christopher Aaron Clark | 2023-09-05 |
| 11727259 | Neural network accelerator with parameters resident on chip | Harshit Khaitan, Ravi Narayanaswami, Dong Hyuk Woo | 2023-08-15 |
| 11501144 | Neural network accelerator with parameters resident on chip | Harshit Khaitan, Ravi Narayanaswami, Dong Hyuk Woo | 2022-11-15 |
| 11422801 | Neural network compute tile | Ravi Narayanaswami, Harshit Khaitan, Dong Hyuk Woo | 2022-08-23 |
| 11379707 | Neural network instruction set architecture | Ravi Narayanaswami, Dong Hyuk Woo, Harshit Khaitan | 2022-07-05 |
| 11341402 | Neural network crossbar stack | Pierre-Luc Cantin | 2022-05-24 |
| 11275992 | Special purpose neural network training chip | Thomas Norrie, Andrew Everett Phelps, Norman Paul Jouppi | 2022-03-15 |
| 11099772 | Hardware double buffering using a special purpose computational unit | Harshit Khaitan, Ravi Narayanaswami, Dong Hyuk Woo | 2021-08-24 |
| 11061854 | Vector reduction processor | Gregory Michael Thorson, Andrew Everett Phelps | 2021-07-13 |
| 10963780 | Yield improvements for three-dimensionally stacked neural network accelerators | Andreas Nowatzyk | 2021-03-30 |
| 10956537 | Permuting in a matrix-vector processor | Dong Hyuk Woo, Gregory Michael Thorson, Andrew Everett Phelps, Jonathan Ross, Christopher Aaron Clark | 2021-03-23 |
| 10936942 | Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies | Uday Kumar Dasari, Ravi Narayanaswami, Dong Hyuk Woo | 2021-03-02 |
| 10885434 | Alternative loop limits for accessing data in multi-dimensional tensors | Harshit Khaitan, Ravi Narayanaswami, Dong Hyuk Woo | 2021-01-05 |
| 10802956 | Accessing prologue and epilogue data | Harshit Khaitan, Ravi Narayanaswami, Dong Hyuk Woo | 2020-10-13 |
| 10706007 | Vector reduction processor | Gregory Michael Thorson, Andrew Everett Phelps | 2020-07-07 |