Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
JB

John O. Borland — 9 Patents

GEGenus: 3 patents #10 of 76Top 15%
TETel Epion: 3 patents #24 of 54Top 45%
VAVarian Semiconductor Equipment Associates: 1 patents #304 of 513Top 60%
Applied Materials: 1 patents #4,824 of 7,310Top 70%
San Jose, CA: #7,016 of 32,062 inventorsTop 25%
California: #67,547 of 386,348 inventorsTop 20%
Overall (All Time): #535,341 of 4,157,543Top 15%
9 Patents All Time
John O. Borland has been granted 9 US patents while listed as an inventor at Genus. The first was granted in 1990 and the most recent in December 2025. John O. Borland ranks #535,341 of 4,157,543 US inventors in our database (top 12.9%). Patent records list John O. Borland in San Jose, CA, US.

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12485582 Low-dust cutting device for multiple tiles and low-dust scoring device for concrete masonry units Mitch Fairweather 2025-12-02
7410890 Formation of doped regions and/or ultra-shallow junctions in semiconductor materials by gas-cluster ion irradiation Allen R. Kirkpatrick, Sean R. Kirkpatrick, Martin D. Tabat, Thomas G. Tetreault, John Hautala +1 more 2008-08-12
7396745 Formation of ultra-shallow junctions by gas-cluster ion irradiation John Hautala, Wesley Skinner 2008-07-08
7259036 Methods of forming doped and un-doped strained semiconductor materials and semiconductor films by gas-cluster-ion-beam irradiation and materials and film products John Hautala, Wesley Skinner, Martin D. Tabat 2007-08-21
6187643 Simplified semiconductor device manufacturing using low energy high tilt angle and high energy post-gate ion implantation (PoGI) 2001-02-13 $26,824,000
5821589 Method for cmos latch-up improvement by mev billi (buried implanted layer for laternal isolation) plus buried layer implantation 1998-10-13 $310,000
5814866 Semiconductor device having at least one field oxide area and CMOS vertically modulated wells (VMW) with a buried implanted layer for lateral isolation having a first portion below a well, a second portion forming another, adjacent well, and a vertical po 1998-09-29 $415,000
5501993 Method of constructing CMOS vertically modulated wells (VMW) by clustered MeV BILLI (buried implanted layer for lateral isolation) implantation 1996-03-26 $1,644,000
4975385 Method of constructing lightly doped drain (LDD) integrated circuit structure Israel Beinglass 1990-12-04 $3,605,000