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USPTO Patent Rankings Data through Dec 31, 2025
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Bernard Gorowitz — 27 Patents

GE: 20 patents #1,372 of 36,430Top 4%
Lockheed Martin: 7 patents #338 of 6,507Top 6%
Elnora, NY: #1 of 4 inventorsTop 25%
New York: #4,677 of 115,490 inventorsTop 5%
Overall (All Time): #142,059 of 4,157,543Top 4%
27 Patents All Time
Bernard Gorowitz has been granted 27 US patents while listed as an inventor at GE. The first was granted in 1980 and the most recent in October 2001. Bernard Gorowitz ranks #142,059 of 4,157,543 US inventors in our database (top 3.4%). Patent records list Bernard Gorowitz in Elnora, NY, US.

Issued Patents All Time

Showing 1–25 of 27 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
6298551 Methods of forming compliant interface structures with partially open interiors for coupling two electrically conductive contact areas Robert J. Wojnarowski, Barry Scott Whitmore 2001-10-09 $100,290,000
6046410 Interface structures for electronic devices Robert J. Wojnarowski, Barry Scott Whitmore 2000-04-04 $301,769,000
5973908 Structure for thin film capacitors Richard Joseph Saia, Kevin Matthew Durocher 1999-10-26 $130,177,000
5857858 Demountable and repairable low pitch interconnect for stacked multichip modules Robert J. Wojnarowski, Ronald Frank Kolc 1999-01-12 $73,694,000
5757072 Structure for protecting air bridges on semiconductor chips from damage Charles Becker, Renato Guida, Thomas Bert Gorczyca, James Wilson Rose 1998-05-26
5736448 Fabrication method for thin film capacitors Richard Joseph Saia, Kevin Matthew Durocher 1998-04-07 $70,973,000
5699234 Stacking of three dimensional high density interconnect modules with metal edge contacts Richard Joseph Saia, Kevin Matthew Durocher 1997-12-16 $69,479,000
5657537 Method for fabricating a stack of two dimensional circuit modules Richard Joseph Saia, Kevin Matthew Durocher 1997-08-19 $53,331,000
5576925 Flexible multilayer thin film capacitors Paul Alan McConnelee, Michael W. DeVre, Stefan J. Rzad, Ernest W. Litch, III 1996-11-19 $29,765,000
5561085 Structure for protecting air bridges on semiconductor chips from damage Charles Becker, Renato Guida, Thomas Bert Gorczyca, James Wilson Rose 1996-10-01
5527741 Fabrication and structures of circuit modules with flexible interconnect layers Herbert S. Cole, Jr., Raymond Albert Fillion, Ronald Frank Kolc, Robert J. Wojnarowski 1996-06-18
5524339 Method for protecting gallium arsenide mmic air bridge structures Richard Joseph Saia, Kevin Matthew Durocher 1996-06-11
5401687 Process for high density interconnection of substrates and integrated circuit chips containing sensitive structures Herbert S. Cole, Jr., Theresa Ann Sitnik-Nieters 1995-03-28
5391516 Method for enhancement of semiconductor device contact pads Robert J. Wojnarowski 1995-02-21 $9,107,000
5366906 Wafer level integration and testing Robert J. Wojnarowski, Constantine A. Neugebauer, Wolfgang Daum, Eric J. Wildi, Michael Gdula +2 more 1994-11-22 $5,921,000
5303684 Combustion control for producing low NO.sub.x emissions through use of flame spectroscopy Dale M. Brown 1994-04-19 $16,413,000
5279706 Method and apparatus for fabricating a metal interconnection pattern for an integrated circuit module Ernest Wayne Balch, Stanton Earl Weaver, William H. King 1994-01-18 $18,622,000
5257496 Combustion control for producing low NO.sub.x emissions through use of flame spectroscopy Dale M. Brown 1993-11-02 $10,431,000
4998151 Power field effect devices having small cell size and low contact resistance Charles Steven Korman, Krishna Shenai, Bantval J. Baliga, Patricia A. Piacente, Tat-Sing P. Chow +1 more 1991-03-05 $15,927,000
4933742 Metallization contact system for large scale integrated circuits Dale M. Brown, Ronald H. Wilson 1990-06-12 $8,444,000
4871617 Ohmic contacts and interconnects to silicon and method of making same Manjin J. Kim, Dale M. Brown, Simon S. Cohen, Richard Joseph Saia 1989-10-03 $10,849,000
4845050 Method of making mo/tiw or w/tiw ohmic contacts to silicon Manjin J. Kim, Dale M. Brown, Simon S. Cohen, Richard Joseph Saia 1989-07-04
4824802 Method of filling interlevel dielectric via or contact holes in multilevel VLSI metallization structures Dale M. Brown, Richard Joseph Saia 1989-04-25 $7,079,000
4522681 Method for tapered dry etching Richard Joseph Saia 1985-06-11 $3,400,000
4444618 Processes and gas mixtures for the reactive ion etching of aluminum and aluminum alloys Richard Joseph Saia 1984-04-24 $10,857,000