Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7197813 | Method of accurate evaluation on magnetoresistive read element | Naoki Mukoyama, Kenichiro Yamada, Hitoshi Kanai, Manabu Watanabe, Norikazu Ozaki | 2007-04-03 |
| 6526654 | Method of producing double-sided circuit board | Zhiyi Song, Kiyokazu Moriizumi, Norikazu Ozaki | 2003-03-04 |
| 6399897 | Multi-layer wiring substrate | Misao Umematsu, Shunichi Kikuchi, Kiyokazu Moriizumi, Norikazu Ozaki | 2002-06-04 |
| 6185714 | Address trap comparator capable of carrying out high speed fault detecting test | — | 2001-02-06 |
| 6085297 | Single-chip memory system including buffer | — | 2000-07-04 |
| 6057168 | Method for forming bumps using dummy wafer | Kiyotaka Seyama, Hideki Ota, Yasuhiro Usui | 2000-05-02 |
| 5908529 | Multi-layer film substrate and process for production thereof | — | 1999-06-01 |
| 5618636 | Thin film multi-layer structure and method for manufacturing the same | Manabu Watanabe | 1997-04-08 |
| 5562970 | Multilayer circuit structure having projecting via lead | — | 1996-10-08 |
| 5432675 | Multi-chip module having thermal contacts | Haruo Sorimachi, Kiyotaka Seyama, Makoto Sumiyoshi | 1995-07-11 |
| 5422228 | Method of producing thin film multi-layered substrate | — | 1995-06-06 |
| 5415920 | Patterned chromium barrier layer with flange-like structure | Kenji Iida | 1995-05-16 |
| 5378310 | Method of producing conductive pattern layer structure | Kenji Iida | 1995-01-03 |
| 5219639 | Multilayer structure and its fabrication method | Noritoshi Sugawara | 1993-06-15 |
| 5207865 | Multilayer structure and method for fabricating the same | — | 1993-05-04 |
| 4968389 | Method of forming a composite film over the surface of aluminum materials | Kanji Nagashima | 1990-11-06 |