Thomas E. Harrington, III — 37 Patents at D3 Semiconductor

Thomas E. Harrington, III has been granted 37 US patents while listed as an inventor at D3 Semiconductor. The first was granted in 1989 and the most recent in September 2025. Thomas E. Harrington, III ranks #88,321 of 4,157,543 US inventors in our database (top 2.1%). Patent records list Thomas E. Harrington, III in Durham, NC, US.

Issued Patents All Time

Showing 1–25 of 37 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
12426341	Semiconductor devices having gate resistors with low variation in resistance values	Sei-Hyung Ryu	2025-09-23
12376332	Edge termination structures for semiconductor devices	Edward Robert Van Brunt	2025-07-29
12317559	Wide bandgap unipolar/bipolar transistor	—	2025-05-27
12159909	Power semiconductor device with reduced strain	Daniel Jenner Lichtenwalner, Edward Robert Van Brunt, Shadi Sabri, Brett Hull, Brice McPherson +1 more	2024-12-03	$32,549,000
12074079	Wide bandgap semiconductor device with sensor element	Joohyung Kim, Sei-Hyung Ryu, Kijeong Han, Edward Robert Van Brunt	2024-08-27	$13,030,000
11985393	Content-modification system with client-side advertisement caching	Jonathan Sullivan, Remy Spoentgen	2024-05-14	$29,834,000
11900411	Dynamic ad insertion decision-making for linear live TV	Jonathan Sullivan, Yves Greatti, Nico Van de Bovenkamp, Caleb Goertel, Marco Huertas	2024-02-13	$46,227,000
11869948	Power semiconductor device with reduced strain	Daniel Jenner Lichtenwalner, Edward Robert Van Brunt, Shadi Sabri, Brett Hull, Brice McPherson +1 more	2024-01-09	$35,680,000
11769828	Gate trench power semiconductor devices having improved deep shield connection patterns	Sei-Hyung Ryu	2023-09-26	$23,073,000
11664436	Semiconductor devices having gate resistors with low variation in resistance values	Sei-Hyung Ryu	2023-05-30	$23,376,000
11600724	Edge termination structures for semiconductor devices	Edward Robert Van Brunt	2023-03-07	$132,477,000
11190854	Content-modification system with client-side advertisement caching	Jonathan Sullivan, Remy Spoentgen	2021-11-30
10580884	Super junction MOS bipolar transistor having drain gaps	Zhijun Qu	2020-03-03
10134890	Termination region architecture for vertical power transistors	John V. Spohnheimer, Zhijun Qu	2018-11-20
10074735	Surface devices within a vertical power device	Zhijun Qu	2018-09-11
9997455	Device architecture and method for precision enhancement of vertical semiconductor devices	—	2018-06-12
9865727	Device architecture and method for improved packing of vertical field effect devices	Robert K. Yang	2018-01-09
9837358	Source-gate region architecture in a vertical power semiconductor device	—	2017-12-05
9806186	Termination region architecture for vertical power transistors	John V. Spohnheimer, Zhijun Qu	2017-10-31
9755058	Surface devices within a vertical power device	Zhijun Qu	2017-09-05
9589889	Device architecture and method for precision enhancement of vertical semiconductor devices	—	2017-03-07
9496386	Device architecture and method for improved packing of vertical field effect devices	Robert K. Yang	2016-11-15
9117709	Device architecture and method for precision enhancement of vertical semiconductor devices	—	2015-08-25
9117899	Device architecture and method for improved packing of vertical field effect devices	Robert K. Yang	2015-08-25
8987778	On-chip electrostatic discharge protection for a semiconductor device	Yue Zu, Hoang P. Nguyen	2015-03-24	$6,258,000

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Thomas E. Harrington, III — 37 Patents

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