TI

Thomas E. Harrington, III

DS D3 Semiconductor: 12 patents #1 of 4Top 25%
DS Dallas Semiconductor: 11 patents #17 of 116Top 15%
WO Wolfspeed: 9 patents #17 of 187Top 10%
RO Roku: 3 patents #138 of 379Top 40%
MP Maxim Integrated Products: 1 patents #560 of 945Top 60%
📍 Durham, NC: #94 of 4,103 inventorsTop 3%
🗺 North Carolina: #952 of 45,564 inventorsTop 3%
Overall (All Time): #88,483 of 4,157,543Top 3%
37
Patents All Time

Issued Patents All Time

Showing 26–37 of 37 patents

Patent #TitleCo-InventorsDate
7376619 Method and system for rapid tenant screening, lease recommendation, and automatic conversion/transcription of data into lease documents Scott A. Jones, Kevin Adams, Jonathan Harrington 2008-05-20
6306718 Method of making polysilicon resistor having adjustable temperature coefficients Varun Singh, Tanmay Kumar, Roy Hensley, Allan T. Mitchell, Jack Qian 2001-10-23
5688722 CMOS integrated circuit with reduced susceptibility to PMOS punchthrough 1997-11-18
5682051 CMOS integrated circuit with reduced susceptibility to PMOS punchthrough 1997-10-28
5181091 Integrated circuit with improved protection against negative transients Robert D. Lee 1993-01-19
5159426 Integrated circuit with improved battery protection 1992-10-27
5122474 Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough 1992-06-16
4980746 Integrated circuit with improved battery protection 1990-12-25
4950620 Process for making integrated circuit with doped silicon dioxide load elements 1990-08-21
4943537 CMOS integrated circuit with reduced susceptibility to PMOS punchthrough 1990-07-24
4906588 Enclosed buried channel transistor 1990-03-06
4862310 Low leakage battery protection diode structure 1989-08-29