Issued Patents All Time
Showing 151–166 of 166 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6243664 | Methods for maximizing routability in a programmable interconnect matrix having less than full connectability | Stephen M. Douglass, W. Alfred Graf, S. Babar Raza, Sundar Rajan, Shiva Sorooshian Borzin +1 more | 2001-06-05 |
| 6100752 | Method and apparatus for reducing power supply current surges in a charge pump using a delayed clock line | May Lee, Lawrence D. Engh | 2000-08-08 |
| 5986489 | Slew rate control circuit for an integrated circuit | S. Babar Raza, Lin-Shih Liu | 1999-11-16 |
| 5959876 | Single or dual message multilevel analog signal recording and playback system containing independently controlled signal storage segments with externally selectable duration capability | Peter E. Gordon, Bruce O. Jordan, Aditya Raina, Lawrence D. Engh, Carl R. Palmer | 1999-09-28 |
| 5923868 | Methods for maximizing routability in a programmable interconnect matrix having less than full connectability | Stephen M. Douglass, W. Alfred Graf, S. Babar Raza, Sundar Rajan, Shiva Sorooshian Borzin +1 more | 1999-07-13 |
| 5859803 | Non-volatile circuit that disables failed devices | David Sowards, Lawrence D. Engh, Jung Sheng Hoei, May Lee | 1999-01-12 |
| 5848066 | Methods for maximizing routability in a programmable interconnect matrix having less than full connectability | Stephen M. Douglass, W. Alfred Graf, S. Babar Raza, Sundar Rajan, Shiva Sorooshian Borzin +1 more | 1998-12-08 |
| 5821794 | Clock distribution architecture and method for high speed CPLDs | Donald A. Krall, S. Babar Raza | 1998-10-13 |
| 5740106 | Apparatus and method for nonvolatile configuration circuit | — | 1998-04-14 |
| 5701092 | OR array architecture for a programmable logic device | Norman P. Taffe, Stephen M. Douglass | 1997-12-23 |
| 5689686 | Methods for maximizing routability in a programmable interconnect matrix having less than full connectability | Stephen M. Douglass, W. Alfred Graf, S. Babar Raza, Sundar Rajan, Shiva Sorooshian Borzin +1 more | 1997-11-18 |
| 5654652 | High-speed ratio CMOS logic structure with static and dynamic pullups and/or pulldowns using feedback | S. Babar Raza | 1997-08-05 |
| 5621338 | High speed configuration independent programmable macrocell | Lin-Shih Liu, Syed Babar Raza, George M. Ansel, Stephen M. Douglass, Jeffery Scott Hunt | 1997-04-15 |
| 5502403 | High speed configuration independent programmable macrocell | Lin-Shih Liu, Syed Babar Raza, George M. Ansel, Stephen M. Douglass, Jeffery Scott Hunt | 1996-03-26 |
| 5467029 | OR array architecture for a programmable logic device | Norman P. Taffe, Stephen M. Douglass | 1995-11-14 |
| 5345112 | Integrated circuit with programmable speed/power adjustment | S. Barbar Raza | 1994-09-06 |