Issued Patents All Time
Showing 101–125 of 166 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8274812 | Write and erase scheme for resistive memory device | Sung Hyun Jo | 2012-09-25 |
| 8174889 | Programming memory devices | Dzung H. Nguyen, Benjamin Louie, Aaron Yip, Jin-Man Han | 2012-05-08 |
| 8164951 | Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling | Aaron Yip | 2012-04-24 |
| 8134853 | High read speed electronic memory with serial array transistors | Richard Fastow | 2012-03-13 |
| 8064251 | Memory device and method having charge level assignments selected to minimize signal coupling | — | 2011-11-22 |
| 8045392 | Multiple level programming in a non-volatile memory device | — | 2011-10-25 |
| 8040738 | Method and apparatus for performing semiconductor memory operations | Imran Khan, Chieu Yin Chia | 2011-10-18 |
| 7995385 | Memory array of pairs of nonvolatile memory cells using Fowler-Nordheim programming and erasing | Michael Achter, Harry Kuo | 2011-08-09 |
| 7894267 | Deterministic programming algorithm that provides tighter cell distributions with a reduced number of programming pulses | Michael Achter, Harry Kuo | 2011-02-22 |
| 7872916 | Deterministic-based programming in memory | Fatima Bathul, Darlene Hamilton, Michael Achter | 2011-01-18 |
| 7869281 | Reading electronic memory utilizing relationships between cell state distributions | — | 2011-01-11 |
| 7835189 | High accuracy adaptive programming | Michael Achter | 2010-11-16 |
| 7773412 | Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling | Aaron Yip | 2010-08-10 |
| 7697324 | Non-volatile memory device and method having bit-state assignments selected to minimize signal coupling | — | 2010-04-13 |
| 7688630 | Programming memory devices | Dzung H. Nguyen, Benjamin Louie, Aaron Yip, Jin-Man Han | 2010-03-30 |
| 7602639 | Reading electronic memory utilizing relationships between cell state distributions | — | 2009-10-13 |
| 7583070 | Zero power start-up circuit for self-bias circuit | — | 2009-09-01 |
| 7567457 | Nonvolatile memory array architecture | Harry Kuo, Michael Achter | 2009-07-28 |
| 7558101 | Scan sensing method that improves sensing margins | Michael Achter | 2009-07-07 |
| 7535767 | Reading multi-cell memory devices utilizing complementary bit information | Michael Achter | 2009-05-19 |
| 7505323 | Programming memory devices | Dzung H. Nguyen, Benjamin Louie, Aaron Yip, Jin-Man Han | 2009-03-17 |
| 7499329 | Flash memory array using adjacent bit line as source | — | 2009-03-03 |
| 7486530 | Method of comparison between cache and data register for non-volatile memory | Hendrik Hartono, Benjamin Louie, Aaron Yip | 2009-02-03 |
| 7457156 | NAND flash depletion cell structure | — | 2008-11-25 |
| 7457155 | Non-volatile memory device and method having bit-state assignments selected to minimize signal coupling | — | 2008-11-25 |