Issued Patents All Time
Showing 51–75 of 166 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9601194 | NAND array comprising parallel transistor and two-terminal switching device | — | 2017-03-21 |
| 9600410 | ReRAM based NAND like architecture with configurable page size | Cliff Zitlaw | 2017-03-21 |
| RE46335 | Switching device having a non-linear element | Wei Lu, Sung Hyun Jo | 2017-03-07 |
| 9576616 | Non-volatile memory with overwrite capability and low write amplification | Sang Thanh Nguyen | 2017-02-21 |
| 9570678 | Resistive RAM with preferental filament formation region and methods | Sung Hyun Jo | 2017-02-14 |
| 9524247 | Fractured erase system and method | Clifford Alan Zitlaw | 2016-12-20 |
| 9460788 | Non-volatile memory cell utilizing volatile switching two terminal device and a MOS transistor | Sung Hyun Jo | 2016-10-04 |
| 9437297 | Write and erase scheme for resistive memory device | Sung Hyun Jo | 2016-09-06 |
| 9431109 | Parallel bitline nonvolatile memory employing channel-based processing technology | Richard Fastow | 2016-08-30 |
| 9385319 | Filamentary based non-volatile resistive memory device and method | Sung Hyun Jo | 2016-07-05 |
| 9362499 | Three dimension programmable resistive random accessed memory array with shared bitline and method | Harry Yue Gee, Sung Hyun Jo, Scott Brad Herner | 2016-06-07 |
| 9362293 | CT-NOR differential bitline sensing architecture | Richard Fastow, Lei Xue | 2016-06-07 |
| 9355717 | Memory array with embedded source line driver and improved voltage regularity | Sang Thanh Nguyen | 2016-05-31 |
| 9324942 | Resistive memory cell with solid state diode | Tanmay Kumar, Sung Hyun Jo | 2016-04-26 |
| 9312007 | Memory device and method having charge level assignments selected to minimize signal coupling | — | 2016-04-12 |
| 9280421 | Error correction for flash memory | Ping Hou | 2016-03-08 |
| 9191000 | Field programmable gate array utilizing two-terminal non-volatile memory | Sang Thanh Nguyen, Tanmay Kumar | 2015-11-17 |
| 9054702 | Field programmable gate array utilizing two-terminal non-volatile memory | Sang Thanh Nguyen, Tanmay Kumar | 2015-06-09 |
| 9047939 | Circuit for concurrent read operation and method therefor | Harry Kuo | 2015-06-02 |
| 9013911 | Memory array architecture with two-terminal memory cells | — | 2015-04-21 |
| 9001552 | Programming a RRAM method and apparatus | Sang Thanh Nguyen, Layne Armijo | 2015-04-07 |
| 8988927 | Non-volatile variable capacitive device including resistive memory cell | Sung Hyun Jo | 2015-03-24 |
| 8982647 | Resistive random access memory equalization and sensing | Sang Thanh Nguyen | 2015-03-17 |
| 8984238 | Fractured erase system and method | Clifford Alan Zitlaw | 2015-03-17 |
| 8975609 | Three dimension programmable resistive random accessed memory array with shared bitline and method | Harry Yue Gee, Sung Hyun Jo, Scott Brad Herner | 2015-03-10 |