MM

Michael Moriarty

CC Compaq Computer: 18 patents #23 of 1,604Top 2%
BS Breakingpoint Systems: 8 patents #3 of 14Top 25%
TB The Boeing: 7 patents #1,574 of 15,756Top 10%
RI Rockwell International: 4 patents #200 of 2,155Top 10%
DU Duke University: 2 patents #648 of 2,315Top 30%
SA Salesforce: 1 patents #2,629 of 4,319Top 65%
CG Compaq Information Technologies Group: 1 patents #84 of 407Top 25%
HP HP: 1 patents #8,774 of 16,619Top 55%
AS Agere Systems: 1 patents #984 of 1,849Top 55%
📍 Simi Valley, CA: #24 of 1,200 inventorsTop 2%
🗺 California: #10,163 of 386,348 inventorsTop 3%
Overall (All Time): #69,854 of 4,157,543Top 2%
43
Patents All Time

Issued Patents All Time

Showing 26–43 of 43 patents

Patent #TitleCo-InventorsDate
6076139 Multimedia computer architecture with multi-channel concurrent memory access Mark W. Welker, Thomas J. Bonola 2000-06-13
6052744 System and method for transferring concurrent multi-media streams over a loosely coupled I/O bus Thanh T. Tran, Thomas J. Bonola 2000-04-18
5978858 Packet protocol and distributed burst engine Thomas J. Bonola, Michael P. Medina 1999-11-02
5960459 Memory controller having precharge prediction based on processor and PCI bus cycles Gary W. Thome, John E. Larson 1999-09-28
5938739 Memory controller including write posting queues, bus read control logic, and a data contents counter Michael J. Collins, Gary W. Thome, Jens K. Ramsey, John E. Larson 1999-08-17
5819105 System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device Michael J. Collins, John E. Larson, Gary W. Thome 1998-10-06
5813038 Memory controller having precharge prediction based on processor and PC bus cycles Gary W. Thome, John E. Larson 1998-09-22
5778413 Programmable memory controller having two level look-up for memory timing parameter Jeffrey C. Stevens, John E. Larson, Gary W. Thome, Michael J. Collins 1998-07-07
5701433 Computer system having a memory controller which performs readahead operations which can be aborted prior to completion John E. Larson 1997-12-23
5634073 System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation Michael J. Collins, Gary W. Thome, Jens K. Ramsey, John E. Larson 1997-05-27
5634112 Memory controller having precharge prediction based on processor and PCI bus cycles Gary W. Thome, John E. Larson 1997-05-27
5553248 System for awarding the highest priority to a microprocessor releasing a system bus after aborting a locked cycle upon detecting a locked retry signal Maria L. Melo, Jeff W. Wolford, Paul R. Culley, Arnold Thomas Schnell 1996-09-03
5535395 Prioritization of microprocessors in multiprocessor computer systems Roger E. Tipley, Mark Taylor 1996-07-09
5524235 System for arbitrating access to memory with dynamic priority assignment John E. Larson, Michael J. Collins, Gary W. Thome 1996-06-04
5309637 Method of manufacturing a micro-passage plate fin heat exchanger 1994-05-10
4947825 Solar concentrator - radiator assembly 1990-08-14
4523532 Combustion method 1985-06-18
4517165 Combustion method 1985-05-14