WG

Walter J. Ghijsen

CS Cadence Design Systems: 7 patents #204 of 2,263Top 10%
📍 San Jose, CA: #8,424 of 32,062 inventorsTop 30%
🗺 California: #82,707 of 386,348 inventorsTop 25%
Overall (All Time): #720,415 of 4,157,543Top 20%
7
Patents All Time

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDate
10635770 Methods, systems, and computer program products for implementing an electronic design with hybrid analysis techniques Xiaohai Wu, Roland Ruehl, Tao Hu, Yujia Li, An-Chang Deng 2020-04-28
10303828 Integrated circuit simulation with efficient memory usage Jaideep Mukherjee, Saibal Saha, Jianyu Li, Yishan Wang 2019-05-28
10248747 Integrated circuit simulation with data persistency for efficient memory usage Jaideep Mukherjee, Saibal Saha, Jianyu Li, Yishan Wang 2019-04-02
10248745 Integrated circuit simulation with variability analysis for efficient memory usage Jaideep Mukherjee, Saibal Saha, Jianyu Li, Yishan Wang 2019-04-02
9524366 Annotations to identify objects in design generated by high level synthesis (HLS) Yosinori Watanabe, Felice Balarin, Abhinav Tallapally, Michael Meyer, Sherry Solden +2 more 2016-12-20
8856700 Methods, systems, and apparatus for reliability synthesis Yosinori Watanabe, Michael Meyer, Michael T. McNamara, David Van Campenhout 2014-10-07
6381563 System and method for simulating circuits using inline subcircuits Donald J. O'Riordan, Kenneth S. Kundert 2002-04-30