An-Chang Deng — 10 Patents at Cadence Design Systems

An-Chang Deng has been granted 10 US patents while listed as an inventor at Cadence Design Systems. The first was granted in 1999 and the most recent in April 2020. An-Chang Deng ranks #481,000 of 4,157,543 US inventors in our database (top 11.6%). Patent records list An-Chang Deng in Saratoga, CA, US.

Patents per Year

Issued Patents All Time

Showing 1–10 of 10 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
10635770	Methods, systems, and computer program products for implementing an electronic design with hybrid analysis techniques	Xiaohai Wu, Roland Ruehl, Tao Hu, Walter J. Ghijsen, Yujia Li	2020-04-28	$41,966,000
10402532	Methods, systems, and computer program products for implementing an electronic design with electrical analyses with compensation circuit components	Yujia Li, Xiaohai Wu	2019-09-03	$19,172,000
8954917	Method and system for performing fast electrical analysis and simulation of an electronic design for power gates	John Yanjiang Shu, Wei Tian	2015-02-10	$4,435,000
8954908	Fast monte carlo statistical analysis using threshold voltage modeling	Hongzhou Liu, Jushan Xie, Michael Tian	2015-02-10	$4,435,000
8667442	Circuit simulation methodology to calculate leakage current during any mode of circuit operation	Wei Tian, Che-Cheng Lin	2014-03-04	$8,033,000
8595677	Method and system for performing voltage-based fast electrical analysis and simulation of an electronic design	John Yanjiang Shu, Xiaodong Zhang	2013-11-26	$2,893,000
6820243	Hybrid system of static analysis and dynamic simulation for circuit design	An-Jui Shey, Henry Horng-Fei Jyu	2004-11-16	$1,164,000
6577992	Transistor level circuit simulator using hierarchical data	Andrei Tcherniaev, Iouri Feinberg, Walter Chan, Jeh-Fu Tuan	2003-06-10	$3,292,000
6209122	Minimization of circuit delay and power through transistor sizing	Henry Horng-Fei Jyu	2001-03-27	$38,375,000
5880967	Minimization of circuit delay and power through transistor sizing	Henry Horng-Fei Jyu	1999-03-09	$43,140,000