Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10997349 | Incremental chaining in the presence of anchored figures | David Mallon, Kenneth Ferguson, Christopher George Stewart, Kenneth Mackie | 2021-05-04 |
| 10235490 | Methods and systems for centering of pins during instance abutment | David Mallon, Kenneth Ferguson, Monika Bijoy | 2019-03-19 |
| 9690893 | Methods and systems for customizable editing of completed chain of abutted instances | Kenneth Ferguson, Min-Ching Lin, David Mallon | 2017-06-27 |
| 9684761 | Method for representing a photonic waveguide port and port specification | — | 2017-06-20 |
| 9336123 | Method and system for automatically establishing a component description format (CDF) debugging environment | Li-Chien Ting, Serena Chiang Caluya, Chia-Fu Chen | 2016-05-10 |
| 9208277 | Automated adjustment of wire connections in computer-assisted design of circuits | — | 2015-12-08 |
| 9202000 | Implementing designs of guard ring and fill structures from simple unit cells | Regis Colwell, Jeremiah Cessna, Khaled Elgalaind, Haitham Gad, Hsun-Chieh Yu +1 more | 2015-12-01 |
| 9053289 | Method and system for implementing an improved interface for designing electronic layouts | Henry Yu, Simon Simonian, Johannes Grad, Jeff Taraldson | 2015-06-09 |
| 8726209 | Method and system for automatically establishing a component description format (CDF) debugging environment | Li-Chien Ting, Serena Chiang Caluya, Chia-Fu Chen | 2014-05-13 |
| 8694941 | System and method for abutment in the presence of dummy shapes | Olivier Badel, Kenny Ferguson, David Mallon, Ted Paone | 2014-04-08 |
| 8533650 | Annotation management for hierarchical designs of integrated circuits | Bogdan G. Arsintescu | 2013-09-10 |
| 8516404 | Methods, systems, and articles of manufacture for implementing constraint checking windows for an electronic design for multiple-patterning lithography processes | Min Cao, Roland Ruehl | 2013-08-20 |
| 8402417 | Spine selection mode for layout editing | — | 2013-03-19 |
| 8364656 | Method and system for implementing multiuser cached parameterized cells | Rajan Arora, Randy Bishop, Arnold Ginetti | 2013-01-29 |
| 8046730 | Systems and methods of editing cells of an electronic circuit design | Kenneth Ferguson, Randy Bishop, Arnold Ginetti | 2011-10-25 |
| 8042088 | Method and system for implementing stacked vias | — | 2011-10-18 |
| 7971175 | Method and system for implementing cached parameterized cells | Arnold Ginetti, Randy Bishop | 2011-06-28 |
| 7949987 | Method and system for implementing abstract layout structures with parameterized cells | Arnold Ginetti, Randy Bishop, Rajan Arora | 2011-05-24 |
| 7945890 | Registry for electronic design automation of integrated circuits | Regis Colwell, Alisa Yurovsky, Timothy Rosek | 2011-05-17 |
| 7861205 | Spine selection mode for layout editing | — | 2010-12-28 |
| 7805698 | Methods and systems for physical hierarchy configuration engine and graphical editor | Kenneth Ferguson, Kenneth Mackie, Sravasti G. Nair | 2010-09-28 |