LT

Li-Chien Ting

CS Cadence Design Systems: 5 patents #303 of 2,263Top 15%
📍 Cupertino, CA: #2,327 of 6,989 inventorsTop 35%
🗺 California: #93,399 of 386,348 inventorsTop 25%
Overall (All Time): #848,833 of 4,157,543Top 25%
6
Patents All Time

Issued Patents All Time

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
10437567 System and method for use in physical design processes Shelly Ann Evans, Serena Chiang Caluya, Alexey Nikolaevich Peskov, Pavel Nikolaevich Migachev, Alexander Smirnov +3 more 2019-10-08
9336123 Method and system for automatically establishing a component description format (CDF) debugging environment Gilles S. C. Lamant, Serena Chiang Caluya, Chia-Fu Chen 2016-05-10
9122834 Method of using continuous parameter value updates to realize rapid Pcell evaluation Serena Chiang Caluya 2015-09-01
8726209 Method and system for automatically establishing a component description format (CDF) debugging environment Gilles S. C. Lamant, Serena Chiang Caluya, Chia-Fu Chen 2014-05-13
8719745 Method and system for automatically establishing hierarchical parameterized cell (PCELL) debugging environment Nikolay Vladimirovich Anufriev, Alexey Nikolayevich Peskov, Serena Chiang Caluya, Chia-Fu Chen 2014-05-06
8560109 Method and system for bi-directional communication between an integrated circuit (IC) layout editor and various IC pattern data viewers Aaron Parr, Rodney Rigby, Cody Kyrobie 2013-10-15