Issued Patents All Time
Showing 51–74 of 74 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7308568 | Network interface with double date rate and delay locked loop | Yong Jiang | 2007-12-11 |
| 7134010 | Network interface with double data rate and delay locked loop | Yong Jiang | 2006-11-07 |
| 7068652 | Pointer based binary search engine and method for use in network devices | Somayajulu Pullela, David Billings | 2006-06-27 |
| 7024576 | Network interface using programmable delay and frequency doubler | Yong Jiang | 2006-04-04 |
| 7010535 | Binary search engine and method | David Billings, Mike Jorda | 2006-03-07 |
| 6981058 | System and method for slot based ARL table learning with concurrent table search using write snoop | David Billings | 2005-12-27 |
| 6965945 | System and method for slot based ARL table learning and concurrent table search using range address insertion blocking | David Billings | 2005-11-15 |
| 6934866 | Network interface using programmable delay and frequency doubler | Yong Jiang | 2005-08-23 |
| 6920552 | Network interface with double data rate and delay locked loop | Yong Jiang | 2005-07-19 |
| 6813620 | Binary search engine and method | David Billings, Mike Jorda | 2004-11-02 |
| 6211022 | Field leakage by using a thin layer of nitride deposited by chemical vapor deposition | Radu Barsan, Sunil Mehta | 2001-04-03 |
| 5908308 | Use of borophosphorous tetraethyl orthosilicate (BPTEOS) to improve isolation in a transistor array | Radu Barsan, Sunil Mehta | 1999-06-01 |
| 5801551 | Depletion mode pass gates with controlling decoder and negative power supply for a programmable logic device | — | 1998-09-01 |
| 5789269 | Field implant for semiconductor device | Sunil Mehta | 1998-08-04 |
| 5754471 | Low power CMOS array for a PLD with program and erase using controlled avalanche injection | Jack Peng | 1998-05-19 |
| 5742542 | Non-volatile memory cells using only positive charge to store data | Stewart Logie | 1998-04-21 |
| 5700698 | Method for screening non-volatile memory and programmable logic devices | Radu Barsan | 1997-12-23 |
| 5666309 | Memory cell for a programmable logic device (PLD) avoiding pumping programming voltage above an NMOS threshold | Jack Peng, Chris Schmidt | 1997-09-09 |
| 5646901 | CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors | Bradley A. Sharpe-Geisler, Radu Barsan | 1997-07-08 |
| 5615150 | Control gate-addressed CMOS non-volatile cell that programs through gates of CMOS transistors | Radu Barsan | 1997-03-25 |
| 5604370 | Field implant for semiconductor device | Sunil Mehta | 1997-02-18 |
| 5596524 | CMOS memory cell with gate oxide of both NMOS and PMOS transistors as tunneling window for program and erase | Bradley A. Sharpe-Geisler | 1997-01-21 |
| 5594687 | Completely complementary MOS memory cell with tunneling through the NMOS and PMOS transistors during program and erase | Radu Barsan, Bradley A. Sharpe-Geisler | 1997-01-14 |
| 5587945 | CMOS EEPROM cell with tunneling window in the read path | Jack Peng, Radu Barsan, Sunil Mehta | 1996-12-24 |