Issued Patents All Time
Showing 101–125 of 128 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6537867 | High speed low voltage semiconductor devices and method of fabrication | Ronald L. Freyman, Ross A. Kohler, Omkaram Nalamasu, Mark R. Pinto, Joseph R. Radosevich +2 more | 2003-03-25 |
| 6440816 | Alignment mark fabrication process to limit accumulation of errors in level to level overlay | Reginald Conway Farrow | 2002-08-27 |
| 6383879 | Semiconductor device having a metal gate with a work function compatible with a semiconductor device | Ranbir Singh, Lori Stirling | 2002-05-07 |
| 6380606 | Locos isolation process using a layered pad nitride and dry field oxidation stack and semiconductor device employing the same | David C. Brady, Pradip K. Roy, Hem M. Vaidya | 2002-04-30 |
| 6365511 | Tungsten silicide nitride as a barrier for high temperature anneals to improve hot carrier reliability | Sailesh Mansinh Merchant, Joseph R. Radosevich | 2002-04-02 |
| 6359339 | Multi-layered metal silicide resistor for Si Ic's | Richard W. Gregor, Sailesh Mansinh Merchant, Jaseph R. Radosevich, Pradip K. Roy | 2002-03-19 |
| 6339246 | Tungsten silicide nitride as an electrode for tantalum pentoxide devices | Sailesh Mansinh Merchant, Pradip K. Roy | 2002-01-15 |
| 6335557 | Metal silicide as a barrier for MOM capacitors in CMOS technologies | Sailesh Mansinh Merchant, Joseph R. Radosevich | 2002-01-01 |
| 6331460 | Method of fabricating a mom capacitor having a metal silicide barrier | Sailesh Mansinh Merchant, Joseph R. Radosevich | 2001-12-18 |
| 6320238 | Gate structure for integrated circuit fabrication | Yi Ma, Sailesh Mansinh Merchant, Pradip K. Roy | 2001-11-20 |
| 6309938 | Deuterated bipolar transistor and method of manufacture thereof | — | 2001-10-30 |
| 6303940 | Charge injection transistor using high-k dielectric barrier layer | Marco Mastrapasqua | 2001-10-16 |
| 6281110 | Method for making an integrated circuit including deutrium annealing of metal interconnect layers | Sailesh Mansinh Merchant, Pradip K. Roy | 2001-08-28 |
| 6281138 | System and method for forming a uniform thin gate oxide layer | David C. Brady, Yi Ma, Pradip K. Roy | 2001-08-28 |
| 6252270 | Increased cycle specification for floating-gate and method of manufacture thereof | Richard W. Gregor, Ranbir Singh | 2001-06-26 |
| 6214675 | Method for fabricating a merged integrated circuit device | William T. Cochran, Morgan J. Thoma | 2001-04-10 |
| 6174807 | Method of controlling gate dopant penetration and diffusion in a semiconductor device | Joseph R. Radosevich | 2001-01-16 |
| 6090686 | Locos isolation process using a layered pad nitride and dry field oxidation stack and semiconductor device employing the same | David C. Brady, Pradip K. Roy, Hem M. Vaidya | 2000-07-18 |
| 6087683 | Silicon germanium heterostructure bipolar transistor with indium doped base | Clifford A. King | 2000-07-11 |
| 6025280 | Use of SiD.sub.4 for deposition of ultra thin and controllable oxides | David C. Brady, Yi Ma, Pradip K. Roy | 2000-02-15 |
| 6023093 | Deuterated direlectric and polysilicon film-based semiconductor devices and method of manufacture thereof | Richard W. Gregor | 2000-02-08 |
| 6008091 | Floating gate avalanche injection MOS transistors with high K dielectric control gates | Richard W. Gregor, Pradip K. Roy | 1999-12-28 |
| 5994221 | Method of fabricating aluminum-indium (or thallium) vias for ULSI metallization and interconnects | Sailesh Mansinh Merchant | 1999-11-30 |
| 5982020 | Deuterated bipolar transistor and method of manufacture thereof | — | 1999-11-09 |
| 5821147 | Integrated circuit fabrication | — | 1998-10-13 |