MT

Mark E. Thierbach

AT AT&T: 9 patents #2,000 of 18,772Top 15%
AS Agere Systems: 3 patents #475 of 1,849Top 30%
AG Agere Systems Guardian: 1 patents #274 of 810Top 35%
AT American Telephone And Telegraph: 1 patents #132 of 699Top 20%
AI At & T Ipm: 1 patents #18 of 189Top 10%
BL Bell Telephone Laboratories: 1 patents #567 of 1,445Top 40%
Overall (All Time): #278,839 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7818135 Optimum timing of write and read clock paths Ravi Jammula, Andrew A. Wang 2010-10-19
6801995 Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codes Mazhar M. Alidina, Sivanand Simanapalli 2004-10-05
6530014 Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits Mazhar M. Alidina, Sivanand Simanapalli, Larry R. Tate 2003-03-04
6467035 System and method for performing table look-ups using a multiple data fetch architecture Larry R. Tate 2002-10-15
6148386 Address generator circuity for a circular buffer Douglas J. Rhodes 2000-11-14
6115805 Non-aligned double word fetch buffer Douglas J. Rhodes, Larry R. Tate 2000-09-05
6092179 Core processor with customizable function unit Alan J. Greenberger, Lawrence A. Rigge 2000-07-18
6073228 Modulo address generator for generating an updated address Carl R. Holmqvist, Douglas J. Rhodes, Larry R. Tate 2000-06-06
5802382 Flexible single chip digital processor architecture Alan J. Greenberger, Lawrence A. Rigge 1998-09-01
5559837 Efficient utilization of present state/next state registers David M. Blaker, Marc Stephen Diamondstein, Gregory S. Ellard, Mohammad S. Mobin, Homayoon Sam 1996-09-24
5465275 Efficient utilization of present state/next state registers David M. Blaker, Marc Stephen Diamondstein, Gregory S. Ellard, Mohammad S. Mobin, Homayoon Sam 1995-11-07
5454014 Digital signal processor David M. Blaker, Gregory S. Ellard, Mohammad S. Mobin 1995-09-26
5432804 Digital processor and viterbi decoder having shared memory Marc Stephen Diamondstein, Homayoon Sam 1995-07-11
RE32858 Stored-program control machine Donald E. Blahut, Marc Harrison 1989-02-07
4661922 Programmed logic array with two-level control timing 1987-04-28
4493029 Microprocessor with PLA adapted to implement subroutines 1985-01-08
4399516 Stored-program control machine Donald E. Blahut, Marc Harrison, Michael J. Killian 1983-08-16