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USPTO Patent Rankings Data through Dec 31, 2025
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Mark E. Thierbach — 17 Patents

ATAT&T: 9 patents #2,006 of 18,772Top 15%
ASAgere Systems: 3 patents #475 of 1,849Top 30%
American Telephone And Telegraph: 1 patents #132 of 699Top 20%
AIAt & T Ipm: 1 patents #18 of 189Top 10%
BLBell Telephone Laboratories: 1 patents #567 of 1,445Top 40%
AGAgere Systems Guardian: 1 patents #274 of 810Top 35%
Lincroft, NJ: #13 of 145 inventorsTop 9%
New Jersey: #4,970 of 69,400 inventorsTop 8%
Overall (All Time): #263,971 of 4,157,543Top 7%
17 Patents All Time
Mark E. Thierbach has been granted 17 US patents while listed as an inventor at AT&T. The first was granted in 1983 and the most recent in October 2010. Mark E. Thierbach ranks #263,971 of 4,157,543 US inventors in our database (top 6.3%). Patent records list Mark E. Thierbach in Lincroft, NJ, US.

Issued Patents All Time

Showing 1–17 of 17 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
7818135 Optimum timing of write and read clock paths Ravi Jammula, Andrew A. Wang 2010-10-19
6801995 Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codes Mazhar M. Alidina, Sivanand Simanapalli 2004-10-05
6530014 Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits Mazhar M. Alidina, Sivanand Simanapalli, Larry R. Tate 2003-03-04
6467035 System and method for performing table look-ups using a multiple data fetch architecture Larry R. Tate 2002-10-15
6148386 Address generator circuity for a circular buffer Douglas J. Rhodes 2000-11-14 $30,398,000
6115805 Non-aligned double word fetch buffer Douglas J. Rhodes, Larry R. Tate 2000-09-05 $67,468,000
6092179 Core processor with customizable function unit Alan J. Greenberger, Lawrence A. Rigge 2000-07-18 $62,471,000
6073228 Modulo address generator for generating an updated address Carl R. Holmqvist, Douglas J. Rhodes, Larry R. Tate 2000-06-06 $98,388,000
5802382 Flexible single chip digital processor architecture Alan J. Greenberger, Lawrence A. Rigge 1998-09-01 $28,227,000
5559837 Efficient utilization of present state/next state registers David M. Blaker, Marc Stephen Diamondstein, Gregory S. Ellard, Mohammad S. Mobin, Homayoon Sam 1996-09-24 $4,175,000
5465275 Efficient utilization of present state/next state registers David M. Blaker, Marc Stephen Diamondstein, Gregory S. Ellard, Mohammad S. Mobin, Homayoon Sam 1995-11-07
5454014 Digital signal processor David M. Blaker, Gregory S. Ellard, Mohammad S. Mobin 1995-09-26
5432804 Digital processor and viterbi decoder having shared memory Marc Stephen Diamondstein, Homayoon Sam 1995-07-11
RE32858 Stored-program control machine Donald E. Blahut, Marc Harrison 1989-02-07
4661922 Programmed logic array with two-level control timing 1987-04-28 $123,665,000
4493029 Microprocessor with PLA adapted to implement subroutines 1985-01-08
4399516 Stored-program control machine Donald E. Blahut, Marc Harrison, Michael J. Killian 1983-08-16 $14,013,000