Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6801995 | Method for optimally encoding a set of instruction codes for a digital processor having a plurality of instruction selectable resource types and an associated optimized set of instruction codes | Mazhar M. Alidina, Mark E. Thierbach | 2004-10-05 |
| 6530014 | Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits | Mazhar M. Alidina, Mark E. Thierbach, Larry R. Tate | 2003-03-04 |
| 6446193 | Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture | Mazhar M. Alidina, Larry R. Tate | 2002-09-03 |
| 6272188 | Single-cycle accelerator for extremun state search | Mohammad S. Mobin, Larry R. Tate | 2001-08-07 |
| 6081921 | Bit insertion approach to convolutional encoding | — | 2000-06-27 |
| 6064714 | Shifter capable of split operation | Mazhar M. Alidina, Geoffrey Francis Burns | 2000-05-16 |
| 6029267 | Single-cycle, soft decision, compare-select operation using dual-add processor | Larry R. Tate | 2000-02-22 |
| 6009128 | Metric acceleration on dual MAC processor | Mohammad S. Mobin, Larry R. Tate | 1999-12-28 |
| 6002726 | FM discriminator with automatic gain control for digital signal processors | Xiao-an Wang | 1999-12-14 |
| 5991785 | Determining an extremum value and its index in an array using a dual-accumulation processor | Mazhar M. Alidina | 1999-11-23 |
| 5987490 | Mac processor with efficient Viterbi ACS operation and automatic traceback store | Mazhar M. Alidina | 1999-11-16 |
| 5912908 | Method of efficient branch metric computation for a Viterbi convolutional decoder | Richard Adam Cesari | 1999-06-15 |