Issued Patents All Time
Showing 126–150 of 191 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6818491 | Set of three level concurrent word line bias conditions for a NOR type flash memory array | Hsing-Ya Tsao, Fu-Chang Hsu, Mervyn Wong | 2004-11-16 |
| 6788612 | Flash memory array structure suitable for multiple simultaneous operations | Fu-Chang Hsu, Hsing-Ya Tsao | 2004-09-07 |
| 6788611 | Flash memory array structure suitable for multiple simultaneous operations | Fu-Chang Hsu, Hsing-Ya Tsao | 2004-09-07 |
| 6777292 | Set of three level concurrent word line bias conditions for a NOR type flash memory array | Hsing-Ya Tsao, Fu-Chang Hsu, Mervyn Wong | 2004-08-17 |
| 6757196 | Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device | Hsing-Ya Tsao, Fu-Chang Hsu | 2004-06-29 |
| 6717846 | Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground configuration | Hung-Sheng Chen, Vei-Han Chan | 2004-04-06 |
| 6714457 | Parallel channel programming scheme for MLC flash memory | Fu-Chang Hsu, Hsing-Ya Tsao | 2004-03-30 |
| 6687154 | Highly-integrated flash memory and mask ROM array architecture | Fu-Chang Hsu | 2004-02-03 |
| 6680859 | Logic process DRAM | Winston Lee, Sehat Sutardja | 2004-01-20 |
| 6660585 | Stacked gate flash memory cell with reduced disturb conditions | Hsing-Ya Tsao, Vei-Han Chan, Hung-Sheng Chen, Fu-Chang Hsu | 2003-12-09 |
| 6628563 | Flash memory array for multiple simultaneous operations | Fu-Chang Hsu, Hsing-Ya Tsao | 2003-09-30 |
| 6620682 | Set of three level concurrent word line bias conditions for a nor type flash memory array | Hsing-Ya Tsao, Fu-Chang Hsu, Mervyn Wong | 2003-09-16 |
| 6584034 | Flash memory array structure suitable for multiple simultaneous operations | Fu-Chang Hsu, Hsing-Ya Tsao | 2003-06-24 |
| 6574152 | Circuit design for accepting multiple input voltages for flash EEPROM memory operations | Fu-Chang Hsu, Hsing-Ya Tsao | 2003-06-03 |
| 6570781 | Logic process DRAM | Winston Lee, Sehat Sutardja | 2003-05-27 |
| 6563742 | Method to turn a flash memory into a versatile, low-cost multiple time programmable EPROM | Tam Tran | 2003-05-13 |
| 6556481 | 3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell | Fu-Chang Hsu, Hsing-Ya Tsao, Mervyn Wong | 2003-04-29 |
| 6515910 | Bit-by-bit Vt-correction operation for nonvolatile semiconductor one-transistor cell, nor-type flash EEPROM | Hsing-Ya Tsao, Tam Tran, Fu-Chang Hsu | 2003-02-04 |
| 6498752 | Three step write process used for a nonvolatile NOR type EEPROM memory | Fu-Chang Hsu, Hsing-Ya Tsao | 2002-12-24 |
| 6381670 | Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation | Hsing-Ya Tsao, Fu-Chang Hsu, Wen-Tan Fan | 2002-04-30 |
| RE37419 | Flash memory array and decoding architecture | Fu-Change Hsu, Hsing-Ya Tsao | 2001-10-23 |
| 6275417 | Multiple level flash memory | Fu-Chang Hsu, Hsing-Ya Tsao | 2001-08-14 |
| 6262622 | Breakdown-free high voltage input circuitry | Fu-Chang Hsu, Hsing-Ya Tsao, Vei-Han Chan, Hung-Sheng Chen | 2001-07-17 |
| 6258668 | Array architecture and process flow of nonvolatile memory devices for mass storage applications | Hung-Sheng Chen, Vei-Han Chan | 2001-07-10 |
| 6240027 | Approach to provide high external voltage for flash memory erase | Fu-Chang Hsu, Mike Chen | 2001-05-29 |