Issued Patents All Time
Showing 26–50 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7120064 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Fu-Chang Hsu, Han-Rei Ma, Koucheng Wu | 2006-10-10 |
| 7110302 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Fu-Chang Hsu, Han-Rei Ma, Koucheng Wu | 2006-09-19 |
| 7102929 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Fu-Chang Hsu, Han-Rei Ma, Koucheng Wu | 2006-09-05 |
| 7075826 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Fu-Chang Hsu, Han-Rei Ma, Koucheng Wu | 2006-07-11 |
| 7064978 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Fu-Chang Hsu, Han-Rei Ma | 2006-06-20 |
| 6906376 | EEPROM cell structure and array architecture | Fu-Chang Hsu | 2005-06-14 |
| 6862223 | MONOLITHIC, COMBO NONVOLATILE MEMORY ALLOWING BYTE, PAGE AND BLOCK WRITE WITH NO DISTURB AND DIVIDED-WELL IN THE CELL ARRAY USING A UNIFIED CELL STRUCTURE AND TECHNOLOGY WITH A NEW SCHEME OF DECODER AND LAYOUT | Peter Wung Lee, Fu-Chang Hsu, Han-Rei Ma, Koucheng Wu | 2005-03-01 |
| 6850438 | Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations | Peter Wung Lee, Fu-Chang Hsu, Han-Rei Ma | 2005-02-01 |
| 6818491 | Set of three level concurrent word line bias conditions for a NOR type flash memory array | Peter Wung Lee, Fu-Chang Hsu, Mervyn Wong | 2004-11-16 |
| 6788611 | Flash memory array structure suitable for multiple simultaneous operations | Fu-Chang Hsu, Peter Wung Lee | 2004-09-07 |
| 6788612 | Flash memory array structure suitable for multiple simultaneous operations | Fu-Chang Hsu, Peter Wung Lee | 2004-09-07 |
| 6777292 | Set of three level concurrent word line bias conditions for a NOR type flash memory array | Peter Wung Lee, Fu-Chang Hsu, Mervyn Wong | 2004-08-17 |
| 6757196 | Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device | Peter Wung Lee, Fu-Chang Hsu | 2004-06-29 |
| 6714457 | Parallel channel programming scheme for MLC flash memory | Fu-Chang Hsu, Peter Wung Lee | 2004-03-30 |
| 6660585 | Stacked gate flash memory cell with reduced disturb conditions | Peter Wung Lee, Vei-Han Chan, Hung-Sheng Chen, Fu-Chang Hsu | 2003-12-09 |
| 6628563 | Flash memory array for multiple simultaneous operations | Fu-Chang Hsu, Peter Wung Lee | 2003-09-30 |
| 6620682 | Set of three level concurrent word line bias conditions for a nor type flash memory array | Peter Wung Lee, Fu-Chang Hsu, Mervyn Wong | 2003-09-16 |
| 6584034 | Flash memory array structure suitable for multiple simultaneous operations | Fu-Chang Hsu, Peter Wung Lee | 2003-06-24 |
| 6574152 | Circuit design for accepting multiple input voltages for flash EEPROM memory operations | Peter Wung Lee, Fu-Chang Hsu | 2003-06-03 |
| 6556481 | 3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell | Fu-Chang Hsu, Peter Wung Lee, Mervyn Wong | 2003-04-29 |
| 6515910 | Bit-by-bit Vt-correction operation for nonvolatile semiconductor one-transistor cell, nor-type flash EEPROM | Peter Wung Lee, Tam Tran, Fu-Chang Hsu | 2003-02-04 |
| 6498752 | Three step write process used for a nonvolatile NOR type EEPROM memory | Fu-Chang Hsu, Peter Wung Lee | 2002-12-24 |
| 6381670 | Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation | Peter Wung Lee, Fu-Chang Hsu, Wen-Tan Fan | 2002-04-30 |
| RE37419 | Flash memory array and decoding architecture | Fu-Change Hsu, Peter Wung Lee | 2001-10-23 |
| 6275417 | Multiple level flash memory | Peter Wung Lee, Fu-Chang Hsu | 2001-08-14 |