Issued Patents All Time
Showing 51–75 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6262622 | Breakdown-free high voltage input circuitry | Peter Wung Lee, Fu-Chang Hsu, Vei-Han Chan, Hung-Sheng Chen | 2001-07-17 |
| 6181607 | Reversed split-gate cell array | Peter Wung Lee, Fu-Chang Hsu | 2001-01-30 |
| 6160737 | Bias conditions for repair, program and erase operations of non-volatile memory | Fu-Chang Hsu, Peter Wung Lee | 2000-12-12 |
| 6134150 | Erase condition for flash memory | Fu-Chang Hsu, Peter Wung Lee, Vei-Han Chan, Hung-Sheng Chen | 2000-10-17 |
| 6031765 | Reversed split-gate cell array | Peter Wung Lee, Fu-Chang Hsu | 2000-02-29 |
| 6023188 | Positive/negative high voltage charge pump system | Peter Wung Lee, Fu-Chang Hsu | 2000-02-08 |
| 6009022 | Node-precise voltage regulation for a MOS memory system | Peter Wung Lee, Fu-Chang Hsu | 1999-12-28 |
| 5978283 | Charge pump circuits | Fu-Chang Hsu, Peter Wung Lee | 1999-11-02 |
| 5978277 | Bias condition and X-decoder circuit of flash memory array | Fu-Chang Hsu, Peter Wung Lee | 1999-11-02 |
| 5953250 | Flash memory array and decoding architecture | Fu-Chang Hsu, Peter Wung Lee | 1999-09-14 |
| 5930826 | Flash memory protection attribute status bits held in a flash memory array | Peter Wung Lee, Fu-Chang Hsu | 1999-07-27 |
| 5920503 | Flash memory with novel bitline decoder and sourceline latch | Peter Wung Lee, Fu-Chang Hsu | 1999-07-06 |
| 5917757 | Flash memory with high speed erasing structure using thin oxide semiconductor devices | Peter Wung Lee, Fu-Chang Hsu | 1999-06-29 |
| 5914896 | Flash memory with high speed erasing structure using thin oxide and thick oxide semiconductor devices | Peter Wung Lee, Fu-Chang Hsu | 1999-06-22 |
| 5859571 | Frequency trimmable oscillator and frequency multiplier | Peter Wung Lee, Fu-Chang Hsu | 1999-01-12 |
| 5856945 | Method for preventing sub-threshold leakage in flash memory cells to achieve accurate reading, verifying, and fast over-erased Vt correction | Peter Wung Lee, Fu-Chang Hsu | 1999-01-05 |
| 5856942 | Flash memory array and decoding architecture | Peter Wung Lee, Fu-Chang Hsu | 1999-01-05 |
| 5848000 | Flash memory address decoder with novel latch structure | Peter Wung Lee, Fu-Chang Hsu | 1998-12-08 |
| 5835420 | Node-precise voltage regulation for a MOS memory system | Peter Wung Lee, Fu-Chang Hsu | 1998-11-10 |
| 5822252 | Flash memory wordline decoder with overerase repair | Peter Wung Lee, Fu-Chang Hsu | 1998-10-13 |
| 5796657 | Flash memory with flexible erasing size from multi-byte to multi-block | Peter Wung Lee, Fu-Chang Hsu | 1998-08-18 |
| 5777923 | Flash memory read/write controller | Peter Wung Lee, Fu-Chang Hsu | 1998-07-07 |
| 5777924 | Flash memory array and decoding architecture | Peter Wung Lee, Fu-Chang Hsu | 1998-07-07 |
| 5774396 | Flash memory with row redundancy | Peter Wung Lee, Fu-Chang Hsu | 1998-06-30 |
| 5768193 | Bit-refreshable method and circuit for refreshing a nonvolatile flash memory | Peter Wung Lee, Fu-Chang Hsu | 1998-06-16 |