Issued Patents All Time
Showing 51–75 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8335108 | Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array | Peter Wung Lee | 2012-12-18 |
| 8331150 | Integrated SRAM and FLOTOX EEPROM memory device | Peter Wung Lee | 2012-12-11 |
| 8295087 | Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS | Peter Wung Lee, Hsing-Ya Tsao | 2012-10-23 |
| 8289775 | Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array | Peter Wung Lee, Hsing-Ya Tsao | 2012-10-16 |
| 8274829 | Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/− 10V BVDS | Peter Wung Lee, Hsing-Ya Tsao | 2012-09-25 |
| 8237212 | Nonvolatile memory with a unified cell structure | Peter Wung Lee, Hsing-Ya Tsao, Han-Rei Ma, Koucheng Wu | 2012-08-07 |
| 8233320 | High speed high density NAND-based 2T-NOR flash memory design | Peter Wung Lee | 2012-07-31 |
| 8149622 | Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storage | Peter Wung Lee, Kesheng Wang | 2012-04-03 |
| 8120959 | NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same | Peter Wung Lee | 2012-02-21 |
| 8072811 | NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array | Peter Wung Lee, Hsing-Ya Tsao | 2011-12-06 |
| 7915092 | Nonvolatile memory with a unified cell structure | Peter Wung Lee, Hsing-Ya Tsao, Han-Rei Ma, Koucheng Wu | 2011-03-29 |
| 7855912 | Circuit and method for multiple-level programming, reading, and erasing dual-sided nonvolatile memory cell | Peter Wung Lee | 2010-12-21 |
| 7830713 | Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array | Peter Wung Lee | 2010-11-09 |
| 7688612 | Bit line structure for a multilevel, dual-sided nonvolatile memory cell array | Peter Wung Lee | 2010-03-30 |
| 7636252 | Nonvolatile memory with a unified cell structure | Peter Wung Lee, Hsing-Ya Tsao, Han-Rei Ma, Koucheng Wu | 2009-12-22 |
| 7372736 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Hsing-Ya Tsao, Han-Rei Ma | 2008-05-13 |
| 7349257 | Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations | Peter Wung Lee, Hsing-Ya Tsao, Han-Rei Ma | 2008-03-25 |
| 7339824 | Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations | Peter Wung Lee, Hsing-Ya Tsao, Han-Rei Ma | 2008-03-04 |
| 7324384 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Hsing-Ya Tsao, Han-Rei Ma, Koucheng Wu | 2008-01-29 |
| 7289366 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Hsing-Ya Tsao, Han-Rei Ma | 2007-10-30 |
| 7283401 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Hsing-Ya Tsao, Han-Rei Ma | 2007-10-16 |
| 7154783 | Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations | Peter Wung Lee, Hsing-Ya Tsao, Han-Rei Ma | 2006-12-26 |
| 7149120 | Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations | Peter Wung Lee, Hsing-Ya Tsao, Han-Rei Ma | 2006-12-12 |
| 7120064 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Hsing-Ya Tsao, Han-Rei Ma, Koucheng Wu | 2006-10-10 |
| 7110302 | Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout | Peter Wung Lee, Hsing-Ya Tsao, Han-Rei Ma, Koucheng Wu | 2006-09-19 |