Issued Patents All Time
Showing 26–50 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10109363 | CMOS anti-fuse cell | — | 2018-10-23 |
| 10008265 | Method and apparatus for providing three-dimensional integrated nonvolatile memory (NVM) and dynamic random access memory (DRAM) memory device | — | 2018-06-26 |
| 9972392 | SONOS byte-erasable EEPROM | — | 2018-05-15 |
| 9928911 | Method and apparatus for providing multi-page read and write using SRAM and nonvolatile memory devices | — | 2018-03-27 |
| 9793001 | CMOS anti-fuse cell | — | 2017-10-17 |
| 9761310 | Method and apparatus for storing information using a memory able to perform both NVM and DRAM functions | — | 2017-09-12 |
| 9715933 | Dual function hybrid memory cell | — | 2017-07-25 |
| 9704577 | Two transistor SONOS flash memory | — | 2017-07-11 |
| 9063849 | Different types of memory integrated in one chip by using a novel protocol | Peter Wung Lee | 2015-06-23 |
| 8996785 | NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface | Peter Wung Lee, Kesheng Wang | 2015-03-31 |
| 8933500 | EEPROM-based, data-oriented combo NVM design | Peter Wung Lee | 2015-01-13 |
| 8917551 | Flexible 2T-based fuzzy and certain matching arrays | Peter Wung Lee | 2014-12-23 |
| 8837221 | Write bias condition for 2T-string NOR flash cell | Peter Wung Lee | 2014-09-16 |
| 8809148 | EEPROM-based, data-oriented combo NVM design | Peter Wung Lee | 2014-08-19 |
| 8775719 | NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface | Peter Wung Lee, Kesheng Wang | 2014-07-08 |
| 8773903 | High speed high density nand-based 2T-NOR flash memory design | Peter Wung Lee | 2014-07-08 |
| 8634254 | Single-polycrystalline silicon electrically erasable and programmable memory device of varied gate oxide thickness, using PIP or MIM coupling capacitor for cell size reduction and simultaneous VPP and VNN for write voltage reduction | Peter Wung Lee | 2014-01-21 |
| 8634241 | Universal timing waveforms sets to improve random access read and write speed of memories | Peter Wung Lee, Hsing-Ya Tsao | 2014-01-21 |
| 8559232 | DRAM-like NVM memory array and sense amplifier design for high temperature and high endurance operation | Peter Wung Lee | 2013-10-15 |
| 8531885 | NAND-based 2T2b NOR flash array with a diode connection to cell's source node for size reduction using the least number of metal layers | Peter Wung Lee | 2013-09-10 |
| 8472251 | Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device | Peter Wung Lee | 2013-06-25 |
| 8462553 | Cell array for highly-scalable, byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory | Peter Wung Lee | 2013-06-11 |
| 8455923 | Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device | Peter Wung Lee, Han-Rei Ma | 2013-06-04 |
| 8355287 | Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device | Peter Wung Lee | 2013-01-15 |
| 8345481 | NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array | Peter Wung Lee, Hsing-Ya Tsao | 2013-01-01 |