Issued Patents All Time
Showing 26–32 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6485654 | Method of fabricating self-aligned contacts | Shea-Jue Wang | 2002-11-26 |
| 6420248 | Double gate oxide layer method of manufacture | Shea-Jue Wang | 2002-07-16 |
| 6358831 | Method for forming a top interconnection level and bonding pads on an integrated circuit chip | Yuan-Lung Liu | 2002-03-19 |
| 6284642 | Integrated method of damascene and borderless via process | Chao-Bao Cheng, Kuo-Chin Hsu | 2001-09-04 |
| 6040223 | Method for making improved polysilicon FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer for more reliable integrated circuits | Jyh-Feng Lin, Ming-Shu Yen, Su-Ying Su, Fu-Ying Chiu, Chien-Hung Lin | 2000-03-21 |
| 6015751 | Self-aligned connection to underlayer metal lines through unlanded via holes | — | 2000-01-18 |
| 5801094 | Dual damascene process | Tri-Rung Yew, Water Lur, Shih-Wei Sun | 1998-09-01 |