Issued Patents All Time
Showing 51–72 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6072725 | Method of erasing floating gate capacitor used in voltage regulator | Binh Quang Le, Shane Hollmer | 2000-06-06 |
| 6055366 | Methods and apparatus to perform high voltage electrical rule check of MOS circuit design | Binh Quang Le, Shane Hollmer, Alexius H. Tan | 2000-04-25 |
| 6009014 | Erase verify scheme for NAND flash | Shane Hollmer, Chung-You Hu, Binh Quang Le, Jonathan S. Su, Ravi Prakash Gutala +1 more | 1999-12-28 |
| 6005804 | Split voltage for NAND flash | Shane Hollmer, Binh Quang Le | 1999-12-21 |
| 5999452 | Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for NAND array flash memory | Mike Van Buskirk, Shane Hollmer, Binh Quang Le, Shoichi Kawamura, Chung-You Hu +3 more | 1999-12-07 |
| 5995417 | Scheme for page erase and erase verify in a non-volatile memory array | Michael Chung, Shane Hollmer, Vincent Leung, Binh Quang Le, Masaru Yano | 1999-11-30 |
| 5978266 | Array VSS biasing for NAND array programming reliability | Shane Hollmer, Binh Quang Le, Michael Chung | 1999-11-02 |
| 5978267 | Bit line biasing method to eliminate program disturbance in a non-volatile memory device and memory device employing the same | Michael A. Van Buskirk, Shane Hollmer, Michael Chung, Binh Quang Le, Vincent Leung +2 more | 1999-11-02 |
| 5973546 | Charge pump circuit architecture | Binh Quang Le, Shane Hollmer | 1999-10-26 |
| 5955874 | Supply voltage-independent reference voltage circuit | Qimeng Zhou | 1999-09-21 |
| 5939928 | Fast high voltage NMOS pass gate for integrated circuit with high voltage generator | Binh Quang Le, Shane Hollmer | 1999-08-17 |
| 5912489 | Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory | Mike Van Buskirk, Shane Hollmer, Binh Quang Le, Shoichi Kawamura, Chung-You Hu +3 more | 1999-06-15 |
| 5909396 | High voltage NMOS pass gate having supply range, area, and speed advantages | Binh Quang Le, Shane Hollmer, Chung-You Hu, Narbeh Derhacobian | 1999-06-01 |
| 5852576 | High voltage NMOS pass gate for integrated circuit with high voltage generator and flash non-volatile memory device having the pass gate | Binh Quang Le, Shane Hollmer, Shoichi Kawamura, Michael Chung, Vincent Leung +1 more | 1998-12-22 |
| 5844840 | High voltage NMOS pass gate having supply range, area, and speed advantages | Binh Quang Le, Shane Hollmer, Chung-You Hu, Narbeh Derhacobian | 1998-12-01 |
| 5821800 | High-voltage CMOS level shifter | Binh Quang Le, Shoichi Kawamura, Shane Hollmer | 1998-10-13 |
| 5818288 | Charge pump circuit having non-uniform stage capacitance for providing increased rise time and reduced area | Binh Quang Le, Shane Hollmer | 1998-10-06 |
| 5815438 | Optimized biasing scheme for NAND read and hot-carrier write operations | Sameer Haddad | 1998-09-29 |
| 5801579 | High voltage NMOS pass gate for integrated circuit with high voltage generator | Binh Quang Le, Shane Hollmer, Shoichi Kawamura, Michael Chung, Vincent Leung +1 more | 1998-09-01 |
| 5638326 | Parallel page buffer verify or read of cells on a word line using a signal from a reference cell in a flash memory device | Shane Hollmer, Binh Quang Le | 1997-06-10 |
| 4905065 | High density dram trench capacitor isolation employing double epitaxial layers | Asim A. Selcuk, Darrell M. Erb | 1990-02-27 |
| 4534824 | Process for forming isolation slots having immunity to surface inversion | — | 1985-08-13 |