Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9372803 | Method and system for shutting down active core based caches | Srilatha Manne, Lloyd Bircher, Madhu Saravana Sibi Govindan, Yasuko Eckert | 2016-06-21 |
| 9360918 | Power control for multi-core data processor | Srilatha Manne, Sanjay Pant, Youngtaek Kim | 2016-06-07 |
| 9344091 | Die-stacked memory device with reconfigurable logic | Nuwan Jayasena, Gabriel H. Loh, Michael Ignatowski | 2016-05-17 |
| 9331053 | Stacked semiconductor chip device with phase change material | Manish Arora, Nuwan Jayasena, Gabriel H. Loh | 2016-05-03 |
| 9235528 | Write endurance management techniques in the logic layer of a stacked memory | Lisa R. Hsu, Gabriel H. Loh, Michael Ignatowski, Nuwan Jayasena, James M. O'Connor | 2016-01-12 |
| 9218204 | Processing engine for complex atomic operations | James M. O'Connor, Nuwan Jayasena, Gabriel H. Loh | 2015-12-22 |
| 9213585 | Controlling sprinting for thermal capacity boosted systems | Manish Arora, Nuwan Jayasena | 2015-12-15 |
| 9170948 | Cache coherency using die-stacked memory device with logic die | Gabriel H. Loh, Bradford M. Beckmann, Lisa R. Hsu, Michael Ignatowski | 2015-10-27 |
| 9135185 | Die-stacked memory device providing data translation | Gabriel H. Loh, Bradford M. Beckmann, James M. O'Connor, Michael Ignatowski, Lisa R. Hsu +1 more | 2015-09-15 |
| 9110671 | Idle phase exit prediction | Yasuko Eckert, Srilatha Manne, William L. Bircher, Mahdu S. S. Govindan, Manish Arora | 2015-08-18 |
| 8959315 | Multithreaded processor with multiple concurrent pipelines per thread | Erdem Hokenek, Mayan Moudgill, C. John Glossner | 2015-02-17 |
| 8922243 | Die-stacked memory device with reconfigurable logic | Nuwan Jayasena, Gabriel H. Loh, Michael Ignatowski | 2014-12-30 |
| 8918627 | Multithreaded processor with multiple concurrent pipelines per thread | Erdem Hokenek, Mayan Moudgill, C. John Glossner | 2014-12-23 |
| 8892849 | Multithreaded processor with multiple concurrent pipelines per thread | Erdem Hokenek, Mayan Moudgill, C. John Glossner | 2014-11-18 |
| 8762688 | Multithreaded processor with multiple concurrent pipelines per thread | Erdem Hokenek, Mayan Moudgill, C. John Glossner | 2014-06-24 |
| 8074051 | Multithreaded processor with multiple concurrent pipelines per thread | Erdem Hokenek, Mayan Moudgill, C. John Glossner | 2011-12-06 |
| 7962543 | Division with rectangular multiplier supporting multiple precisions and operand types | Carl E. Lemonds, Dimitri Tan | 2011-06-14 |
| 7889086 | Camera arrangement in a motor vehicle | Heiko Schafer | 2011-02-15 |
| 7817205 | Camera array and method for adjusting a lens with respect to the image sensor | Michael Makaruk, Markus Adameck | 2010-10-19 |
| 7797363 | Processor having parallel vector multiply and reduce operations with sequential semantics | Erdem Hokenek, Mayan Moudgill, C. John Glossner | 2010-09-14 |
| 7743084 | Processing unit having multioperand decimal addition | Robert D. Kenney | 2010-06-22 |
| 7593978 | Processor reduction unit for accumulation of multiple operands with or without saturation | Pablo Balzola, C. John Glossner | 2009-09-22 |
| 7546328 | Decimal floating-point adder | John Thompson, Nandini Karra | 2009-06-09 |
| 7475222 | Multi-threaded processor having compound instruction and operation formats | C. John Glossner, Erdem Hokenek, Mayan Moudgill | 2009-01-06 |
| 7467174 | Processing unit having decimal floating-point divider using Newton-Raphson iteration | Liang-Kai Wang | 2008-12-16 |