Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12271818 | Implementation-tuned architecture for neural network processing in a learned transform domain | Kristof Denolf, Alireza Khodamoradi | 2025-04-08 |
| 12067484 | Learning neural networks of programmable device blocks directly with backpropagation | Yaman Umuroglu, Nicholas Fraser, Michaela Blott, Kristof Denolf | 2024-08-20 |
| 11972132 | Data processing engine arrangement in a device | Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Richard L. Walke +3 more | 2024-04-30 |
| 11954359 | Circular buffer architecture using local memories with limited resources | Kristof Denolf, Jack Lo, Louis Coulon | 2024-04-09 |
| 11934932 | Error aware module redundancy for machine learning | Giulio Gambardella, Nicholas Fraser, Ussama Zahid, Michaela Blott | 2024-03-19 |
| 11676004 | Architecture optimized training of neural networks | Kristof Denolf | 2023-06-13 |
| 11573726 | Data processing engine arrangement in a device | Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Richard L. Walke +3 more | 2023-02-07 |
| 11327677 | Data mover circuitry for N-dimensional data in an integrated circuit | Kristof Denolf, Jack Lo | 2022-05-10 |
| 10990552 | Streaming interconnect architecture for data processing engine array | Goran H K Bilski, Peter McColgan, Juan J. Noguera Serra, Baris Ozgul, Jan Langer +4 more | 2021-04-27 |
| 10866753 | Data processing engine arrangement in a device | Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Tim Tuan +3 more | 2020-12-15 |
| 10747690 | Device with data processing engine array | Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Richard L. Walke +3 more | 2020-08-18 |
| 10482054 | AXI-CAPI adapter | Ling Liu, Michaela Blott, Kimon Karras, Thomas Janson | 2019-11-19 |
| 10320918 | Data-flow architecture for a TCP offload engine | Michaela Blott, David Andreas SIDLER, Kimon Karras, Raymond Carley | 2019-06-11 |
| 9711194 | Circuits for and methods of controlling the operation of a hybrid memory system | Michaela Blott, Ling Liu | 2017-07-18 |
| 9519486 | Method of and device for processing data using a pipeline of processing blocks | Michaela Blott, Thomas B. English | 2016-12-13 |
| 9503093 | Virtualization of programmable integrated circuits | Kimon Karras, Michaela Blott | 2016-11-22 |
| 9323457 | Memory arrangement for implementation of high-throughput key-value stores | Michaela Blott, Ling Liu | 2016-04-26 |
| 7929609 | Motion estimation and/or compensation | Abraham Karel Riemens, Robert Jan Schutten, Jeroen Maria Kettenis, Olukayode Ojo | 2011-04-19 |
| 7881320 | Parsing data from multiple digital bitstreams | Paul R. Schumacher | 2011-02-01 |
| 7684278 | Method and apparatus for implementing FIFOs using time-multiplexed memory in an integrated circuit | Paul R. Schumacher, Mark Paluszkiewicz | 2010-03-23 |
| 7669037 | Method and apparatus for communication between a processor and hardware blocks in a programmable logic device | Paul R. Schumacher | 2010-02-23 |
| 7359276 | Multi-port system for communication between processing elements | Robert D. Turney, Paul R. Schumacher | 2008-04-15 |
| 7293258 | Data processor and method for using a data processor with debug circuit | Hendrikus Petrus Elisabeth Vranken, Fransiscus Wilhelmus Sijstermans | 2007-11-06 |
| 7262807 | Signal processing device for providing multiple output images in one pass | Abraham Karel Riemens, Robert Jan Schutten | 2007-08-28 |
| 7010042 | Image processor and image display apparatus provided with such image processor | Abraham Karel Riemens, Robert Jan Schutten | 2006-03-07 |