Issued Patents All Time
Showing 26–50 of 108 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7619441 | Apparatus for interconnecting stacked dice on a programmable integrated circuit | Arifur Rahman | 2009-11-17 |
| 7567997 | Applications of cascading DSP slices | James M. Simkins, Steven P. Young, Jennifer Wong, Alvin Y. Ching | 2009-07-28 |
| 7546408 | Method and apparatus for communication within a programmable device using serial transceivers | Adam P. Donlin | 2009-06-09 |
| 7518398 | Integrated circuit with through-die via interface for die stacking | Arifur Rahman, Stephen M. Trimberger | 2009-04-14 |
| 7509610 | Timing analysis for programmable logic devices fabricated in different Fabs | — | 2009-03-24 |
| 7480690 | Arithmetic circuit with multiplexed addend inputs | James M. Simkins, Steven P. Young, Jennifer Wong, Alvin Y. Ching | 2009-01-20 |
| 7472155 | Programmable logic device with cascading DSP slices | James M. Simkins, Steven P. Young, Jennifer Wong, Alvin Y. Ching | 2008-12-30 |
| 7467175 | Programmable logic device with pipelined DSP slices | James M. Simkins, Steven P. Young, Jennifer Wong, Alvin Y. Ching | 2008-12-16 |
| 7467177 | Mathematical circuit with dynamic rounding | James M. Simkins, Steven P. Young, Jennifer Wong, Alvin Y. Ching | 2008-12-16 |
| 7301824 | Method and apparatus for communication within an integrated circuit | — | 2007-11-27 |
| 7248073 | Configurable logic element with expander structures | Ralph D. Wittig, Sundararajarao Mohan | 2007-07-24 |
| 7240320 | Routing with derivative frame awareness to minimize device programming time and test cost | Stephen M. Trimberger, Austin H. Lesea | 2007-07-03 |
| 7191342 | Methods and circuits for allowing encrypted and unencrypted configuration data to share configuration frames | William S. Carter | 2007-03-13 |
| 7149996 | Reconfigurable multi-stage crossbar | Patrick Lysaght, Delon Levi, Brandon J. Blodget | 2006-12-12 |
| 7145360 | Configurable logic element with expander structures | Ralph D. Wittig, Sundararajarao Mohan | 2006-12-05 |
| 7138828 | FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same | — | 2006-11-21 |
| 7107560 | Method and apparatus for designing custom programmable logic devices | — | 2006-09-12 |
| 7098710 | Multi-speed delay-locked loop | Andrew K. Percey | 2006-08-29 |
| 7068072 | Integrated circuit with interface tile for coupling to a stacked-die second integrated circuit | Robert O. Conn, Steven P. Young, Edel M. Young | 2006-06-27 |
| 7062586 | Method and apparatus for communication within a programmable logic device using serial transceivers | Adam P. Donlin | 2006-06-13 |
| 6960934 | FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same | — | 2005-11-01 |
| 6948147 | Method and apparatus for configuring a programmable logic device using a master JTAG port | Adam P. Donlin | 2005-09-20 |
| 6930510 | FPGA architecture with mixed interconnect resources optimized for fast and low-power routing and methods of utilizing the same | — | 2005-08-16 |
| 6917219 | Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice | — | 2005-07-12 |
| 6911730 | Multi-chip module including embedded transistors within the substrate | — | 2005-06-28 |