Issued Patents All Time
Showing 26–50 of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11809849 | Global modulo allocation in neural network compilation | Hongbin Zheng, Robert Geva | 2023-11-07 |
| 11809981 | Performing hardware operator fusion | Animesh Jain, Tobias Edler Von Koch, Yizhi Liu, Taemin Kim, Jindrich Zejda +3 more | 2023-11-07 |
| 11803736 | Fine-grained sparsity computations in systolic array | Paul Gilbert Meyer, Thiam Khean Hah, Ron Diamant, Vignesh Vivekraja | 2023-10-31 |
| 11797853 | Processing for multiple input data sets | Dana Michelle Vantrease, Ron Diamant, Thomas A. Volpe | 2023-10-24 |
| 11741345 | Multi-memory on-chip computational network | Ron Diamant | 2023-08-29 |
| 11741350 | Efficient utilization of processing element array | Jeffrey T. Huynh, Ron Diamant, Hongbin Zheng, Yizhi Liu, Animesh Jain +5 more | 2023-08-29 |
| 11714992 | Neural network processing based on subgraph recognition | Richard John Heaton, Ron Diamant | 2023-08-01 |
| 11687761 | Improper neural network input detection and handling | Richard John Heaton, Andrea Olgiati, Ron Diamant | 2023-06-27 |
| 11610128 | Neural network training under memory restraint | Sudipta Sengupta, Ron Diamant, Vignesh Vivekraja | 2023-03-21 |
| 11567778 | Neural network operation reordering for parallel execution | Jeffrey T. Huynh, Drazen Borkovic, Jindrich Zejda, Ron Diamant | 2023-01-31 |
| 11568238 | Dynamic processing element array expansion | Ron Diamant, Richard John Heaton | 2023-01-31 |
| 11562554 | Workload reduction for non-maximum suppression operation | Abinash Mohanty | 2023-01-24 |
| 11561833 | Allocation and placement of resources for network computation | Richard John Heaton, Drazen Borkovic, Jindrich Zejda | 2023-01-24 |
| 11500962 | Emulating fine-grained sparsity in a systolic array | Paul Gilbert Meyer, Thiam Khean Hah, Ron Diamant, Vignesh Vivekraja | 2022-11-15 |
| 11475306 | Processing for multiple input data sets | Dana Michelle Vantrease, Ron Diamant, Thomas A. Volpe | 2022-10-18 |
| 11461631 | Scheduling neural network computations based on memory capacity | Dana Michelle Vantrease, Ron Diamant, Thomas A. Volpe | 2022-10-04 |
| 11461662 | Compilation time reduction for memory and compute bound neural networks | Hongbin Zheng, Richard John Heaton | 2022-10-04 |
| 11416736 | Dense digital arithmetic circuitry utilization for fixed-point machine learning | Kevin Nealis | 2022-08-16 |
| 11314842 | Hardware implementation of mathematical functions | Ron Diamant, Mohammad El-Shabani, Sundeep Amirineni, Kenneth Wayne Patton, Willis Wang | 2022-04-26 |
| 11308396 | Neural network layer-by-layer debugging | Jindrich Zejda, Jeffrey T. Huynh, Drazen Borkovic, Se-Jong Oh, Ron Diamant | 2022-04-19 |
| 11294599 | Registers for restricted memory | Ron Diamant, Sundeep Amirineni, Jeffrey T. Huynh | 2022-04-05 |
| 11263517 | Flexible weight expansion | Ron Diamant | 2022-03-01 |
| 11250319 | Circuit architecture with biased randomization | Ron Diamant | 2022-02-15 |
| 11232016 | Debug for computation networks using error detection codes | Jeffrey T. Huynh, Ron Diamant, Sundeep Amirineni | 2022-01-25 |
| 11188302 | Top value computation on an integrated circuit device | Ron Diamant, Richard John Heaton | 2021-11-30 |