Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12361195 | Extending cover properties in formal verification to generate failure traces that reach end-of-test | Hani Assaf, Uri Leder, Yefim Fainstein | 2025-07-15 |
| 12271669 | Executing instruction sequences generated from software interactions as part of formal verification of a design under test | Uri Leder, Ori Ariel, Assaf Fainer, Simaan Bahouth, Itai Kahana | 2025-04-08 |
| 12175178 | Fuzzy scoreboard | Uri Leder | 2024-12-24 |
| 11768990 | Interconnect flow graph for integrated circuit design | Uri Leder, Ori Ariel, Benzi Denkberg, Guy Nakibly | 2023-09-26 |
| 11544436 | Hardware-software interaction testing using formal verification | Uri Leder, Ori Cohen, Benzi Denkberg | 2023-01-03 |
| 11062077 | Bit-reduced verification for memory arrays | — | 2021-07-13 |