Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12271669 | Executing instruction sequences generated from software interactions as part of formal verification of a design under test | Uri Leder, Assaf Fainer, Simaan Bahouth, Max Chvalevsky, Itai Kahana | 2025-04-08 |
| 11768990 | Interconnect flow graph for integrated circuit design | Uri Leder, Max Chvalevsky, Benzi Denkberg, Guy Nakibly | 2023-09-26 |