Issued Patents All Time
Showing 51–61 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7783946 | Scan based computation of a signature concurrently with functional operation | — | 2010-08-24 |
| 7779316 | Method of testing memory array at operational speed using scan | Gaurav Agarwal, Krishna B. Rajan, Paul J. Dickinson | 2010-08-17 |
| 7757133 | Built-in self-test hardware and method for generating memory tests with arbitrary address sequences | — | 2010-07-13 |
| 7657804 | Plesiochronous transmit pin with synchronous mode for testing on ATE | — | 2010-02-02 |
| 7650543 | Plesiochronous receiver pin with synchronous mode for testing on ATE | — | 2010-01-19 |
| 7127640 | On-chip testing of embedded memories using Address Space Identifier bus in SPARC architectures | Chitresh Narasimhaiah | 2006-10-24 |
| 7082560 | Scan capable dual edge-triggered state element for application of combinational and sequential scan test patterns | Ha Pham | 2006-07-25 |
| 6769081 | Reconfigurable built-in self-test engine for testing a reconfigurable memory | — | 2004-07-27 |
| 6658632 | Boundary scan cell architecture with complete set of operational modes for high performance integrated circuits | Sridhar Narayanan | 2003-12-02 |
| 6578168 | Method for operating a boundary scan cell design for high performance I/O cells | Sridhar Narayanan, Gajendra Prasad Singh, Jaya Prakash Samala | 2003-06-10 |
| 6567944 | Boundary scan cell design for high performance I/O cells | Gajendra Prasad Singh, Jaya Prakash Samala, Sridhar Narayanan | 2003-05-20 |