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USPTO Patent Rankings Data through Dec 31, 2025
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Wayne W. Wong — 11 Patents

ACActel: 9 patents #31 of 156Top 20%
Broadcom: 1 patents #5,859 of 9,346Top 65%
San Jose, CA: #5,902 of 32,062 inventorsTop 20%
California: #56,011 of 386,348 inventorsTop 15%
Overall (All Time): #435,149 of 4,157,543Top 15%
11 Patents All Time
Wayne W. Wong has been granted 11 US patents while listed as an inventor at Actel. The first was granted in 2004 and the most recent in May 2016. Wayne W. Wong ranks #435,149 of 4,157,543 US inventors in our database (top 10.5%). Patent records list Wayne W. Wong in San Jose, CA, US.

Issued Patents All Time

Showing 1–11 of 11 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
9344268 Phase alignment architecture for ultra high-speed data path Ali Nazemi, Burak Catli, Kangmin Hu, Hyo Gyuem Rhew, Delong Cui +3 more 2016-05-17
7941685 Delay locked loop for an FPGA architecture William C. Plants, Nikhil Mazumder, Arunangshu Kundu, James D. Joseph 2011-05-10
7558967 Encryption for a stream file in an FPGA integrated circuit 2009-07-07 $895,000
7549138 Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA Shin-Nan Sun 2009-06-16 $1,897,000
7484113 Delay locked loop for an FPGA architecture William C. Plants, Nikhil Mazumder, Arunangshu Kundu, James D. Joseph 2009-01-27 $919,000
7269814 Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA Shin-Nan Sun 2007-09-11 $880,000
7171575 Delay locked loop for and FPGA architecture William C. Plants, Nikhil Mazumder, Arunangshu Kundu, James D. Joseph 2007-01-30 $1,571,000
7111272 Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA Shin-Nan Sun 2006-09-19 $2,582,000
6976185 Delay locked loop for an FPGA architecture William C. Plants, Nikhil Mazumder, Arunangshu Kundu, James D. Joseph 2005-12-13 $2,039,000
6885218 Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA Shin-Nan Sun 2005-04-26 $3,196,000
6718477 Delay locked loop for an FPGA architecture William C. Plants, Nikhil Mazumder, Arunangshu Kundu, James D. Joseph 2004-04-06