Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9147025 | Method for efficient FPGA packing | Wenyi Feng, Jonathan W. Greene, Kristofer Vorwerk, Val Pevzner | 2015-09-29 |
| 7941685 | Delay locked loop for an FPGA architecture | William C. Plants, Nikhil Mazumder, James D. Joseph, Wayne W. Wong | 2011-05-10 |
| 7886130 | Field programmable gate array and microcontroller system-on-a-chip | Arnold Goldfein, William C. Plants, David Hightower | 2011-02-08 |
| 7579869 | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks | Eric A. Sather, William C. Plants | 2009-08-25 |
| 7545168 | Clock tree network in a field programmable gate array | — | 2009-06-09 |
| 7516303 | Field programmable gate array and microcontroller system-on-a-chip | Arnold Goldfein, William C. Plants, David Hightower | 2009-04-07 |
| 7484113 | Delay locked loop for an FPGA architecture | William C. Plants, Nikhil Mazumder, James D. Joseph, Wayne W. Wong | 2009-01-27 |
| 7432733 | Multi-level routing architecture in a field programmable gate array having transmitters and receivers | Venkatesh Narayanan, John McCollum, William C. Plants | 2008-10-07 |
| 7394289 | Synchronous first-in/first-out block memory for a field programmable gate array | Daniel Elftmann, Theodore Speers | 2008-07-01 |
| 7385419 | Dedicated input/output first in/first out module for a field programmable gate array | William C. Plants | 2008-06-10 |
| 7385420 | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks | Eric A. Sather, William C. Plants | 2008-06-10 |
| 7375553 | Clock tree network in a field programmable gate array | — | 2008-05-20 |
| 7227380 | Synchronous first-in/first-out block memory for a field programmable gate array | Daniel Elftmann, Theodore Speers | 2007-06-05 |
| 7199609 | Dedicated input/output first in/first out module for a field programmable gate array | William C. Plants | 2007-04-03 |
| 7171575 | Delay locked loop for and FPGA architecture | William C. Plants, Nikhil Mazumder, James D. Joseph, Wayne W. Wong | 2007-01-30 |
| 7126374 | Multi-level routing architecture in a field programmable gate array having transmitters and receivers | Venkatesh Narayanan, John McCollum, William C. Plants | 2006-10-24 |
| 7102385 | Dedicated input/output first in/first out module for a field programmable gate array | William C. Plants | 2006-09-05 |
| 7075334 | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks | Eric A. Sather, William C. Plants | 2006-07-11 |
| 7069419 | Field programmable gate array and microcontroller system-on-a-chip | Arnold Goldfein, William C. Plants, David Hightower | 2006-06-27 |
| 7049846 | Clock tree network in a field programmable gate array | — | 2006-05-23 |
| 6980028 | Dedicated input/output first in/first out module for a field programmable gate array | William C. Plants | 2005-12-27 |
| 6980027 | Synchronous first-in/first-out block memory for a field programmable gate array | Daniel Elftmann, Theodore Speers | 2005-12-27 |
| 6976185 | Delay locked loop for an FPGA architecture | William C. Plants, Nikhil Mazumder, James D. Joseph, Wayne W. Wong | 2005-12-13 |
| 6946871 | Multi-level routing architecture in a field programmable gate array having transmitters and receivers | Venkatesh Narayanan, John McCollum, William C. Plants | 2005-09-20 |
| 6891396 | Repeatable block producing a non-uniform routing architecture in a field programmable gate array having segmented tracks | Eric A. Sather, William C. Plants | 2005-05-10 |