Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA

Parallel programmable antifuse field programmable gate array device (FPGA) and a method for programming and testing an antifuse FPGA

US Patent 7549138 · Granted Jun 16, 2009

Estimated economic value: $1,897,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Phase alignment architecture for ultra high-speed data path2016
Delay locked loop for an FPGA architecture2011
Clock-generator architecture for a programmable-logic-based system on a chip2009
Encryption for a stream file in an FPGA integrated circuit2009
Clock-generator architecture for a programmable-logic-based system on a chip2009
Delay locked loop for an FPGA architecture2009
Clock-generator architecture for a programmable-logic-based system on a chip2007
Parallel programmable antifuse field programmable gate array device (FPGA) and a2007
Parallel programmable antifuse field programmable gate array device (FPGA) and a2007
Delay locked loop for and FPGA architecture2007
Parallel programmable antifuse field programmable gate array device (FPGA) and a2006
Parallel programmable antifuse field programmable gate array device (FPGA) and a2006