Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12212645 | Reset synchronizing circuit and glitchless clock buffer circuit for preventing start-up failure, and IQ divider circuit | Juyun Lee, Vishnu Kalyanamahadevi Gopalan Jawarlal, Kang Jik Kim, Jae Hyun Park | 2025-01-28 |
| 11804945 | Reset synchronizing circuit and glitchless clock buffer circuit for preventing start-up failure, and IQ divider circuit | Juyun Lee, Vishnu Kalyanamahadevi Gopalan Jawarlal, Kang Jik Kim, Jae Hyun Park | 2023-10-31 |
| 10277210 | Clock skew suppression for time-interleaved clocks | Adesh Garg, Meisam Honarvar Nazari, Jiawen Zhang, Ali Nazemi, Jun Cao | 2019-04-30 |
| 9685969 | Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration | Adesh Garg, Ali Nazemi, Anand J. Vasani, Jiawen Zhang, Jun Cao +3 more | 2017-06-20 |
| 9344268 | Phase alignment architecture for ultra high-speed data path | Ali Nazemi, Burak Catli, Wayne W. Wong, Kangmin Hu, Delong Cui +3 more | 2016-05-17 |
| 8892208 | Closed-loop neural stimulation | Michael P. Flynn, Parag G. Patil, Jaehun Jeong | 2014-11-18 |