Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12212645 | Reset synchronizing circuit and glitchless clock buffer circuit for preventing start-up failure, and IQ divider circuit | Juyun Lee, Kang Jik Kim, Hyo Gyuem Rhew, Jae Hyun Park | 2025-01-28 |
| 11996854 | Method and system for low noise sub-sampling phase lock loop (PLL) architecture with automatic dynamic frequency acquisition | Sushrant Monga | 2024-05-28 |
| 11909407 | Method and system of dynamically controlling reset signal of IQ divider | Praveen Rathee, Sanjeeb Kumar Ghosh, Avneesh Singh Verma | 2024-02-20 |
| 11804945 | Reset synchronizing circuit and glitchless clock buffer circuit for preventing start-up failure, and IQ divider circuit | Juyun Lee, Kang Jik Kim, Hyo Gyuem Rhew, Jae Hyun Park | 2023-10-31 |
| 11728792 | Apparatus and method for in-phase and quadrature phase (IQ) generation | Sumanth Chakkirala | 2023-08-15 |
| 11601116 | System and method for generating sub harmonic locked frequency division and phase interpolation | Gunjan Mandal | 2023-03-07 |
| 11469746 | Integrated device having phase interpolator and input controller thereof | Gunjan Mandal, Avneesh Singh Verma, Sanjeeb Kumar Ghosh | 2022-10-11 |
| 10917076 | Ring oscillator and method for controlling start-up of ring oscillator | Tamal Das, Avneesh Singh Verma, Sanjeeb Kumar Ghosh | 2021-02-09 |