Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11996854 | Method and system for low noise sub-sampling phase lock loop (PLL) architecture with automatic dynamic frequency acquisition | Vishnu Kalyanamahadevi Gopalan Jawarlal | 2024-05-28 |
| 11870614 | Method and system for high speed decision-feedback equalization (DFE) | — | 2024-01-09 |
| 11811566 | Methods and systems for performing adaptive equalization of data | — | 2023-11-07 |
| 11477057 | Quarter rate speculative decision feedback equalizer (DFE) and method for operating thereof | Parin Rajnikant Bhuta, Saikat Hazra, Sanjeeb Kumar Ghosh | 2022-10-18 |
| 10340940 | Variable step switched capacitor based digital to analog converter incorporating higher order interpolation | Robert Bogdan Staszewski | 2019-07-02 |
| 9184748 | Adaptive buffer | — | 2015-11-10 |
| 8736305 | Input and output buffer including a dynamic driver reference generator | — | 2014-05-27 |
| 8044684 | Input and output buffer including a dynamic driver reference generator | — | 2011-10-25 |