Issued Patents 2025
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12424515 | SOIC chip architecture | Fong-Yuan Chang, Chin-Chou Liu, Chin-Her Chien, Cheng-Hung Yeh, Hui Yu Lee +1 more | 2025-09-23 |
| 12277379 | Method and system for generating layout diagram including wiring arrangement | Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue +3 more | 2025-04-15 |
| 12261116 | Backside signal routing | Ching-Yu Huang, Wei-Cheng Lin, Shih-Wei Peng, Jiann-Tyng Tzeng | 2025-03-25 |
| 12230624 | Integrated circuit with mixed row heights | Kam-Tou Sio, Jiann-Tyng Tzeng, Chung-Hsing Wang | 2025-02-18 |
| 12223252 | Through-silicon via in integrated circuit packaging | Fong-Yuan Chang, Chin-Chou Liu, Chin-Her Chien, Cheng-Hung Yeh, Po-Hsiang Huang +2 more | 2025-02-11 |
| 12216981 | System and method for generating layout diagram including wiring arrangement | Fong-Yuan Chang, Chin-Chou Liu, Hui-Zhong Zhuang, Meng-Kai Hsu, Pin-Dai Sue +3 more | 2025-02-04 |