Issued Patents 2025
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12396255 | Multiple back side/buried power rail (BPR) cell including field-effect transistors with air void between two adjacent BPR cells | Te-Hsin Chiu, Jiann-Tyng Tzeng | 2025-08-19 |
| 12388013 | Three dimensional integrated circuit with monolithic inter-tier vias (MIV) | Shih-Wei Peng, Jiann-Tyng Tzeng, Wei-Cheng Lin, Wei-An Lai | 2025-08-12 |
| 12334179 | Cell structures and power routing for integrated circuits | Shih-Wei Peng, Jiann-Tyng Tzeng | 2025-06-17 |
| 12336296 | Semiconductor device including source/drain contact having height below gate stack | Charles Chew-Yuen Young, Chih-Liang Chen, Chih-Ming Lai, Jiann-Tyng Tzeng, Shun Li Chen +3 more | 2025-06-17 |
| 12327786 | Decoupling capacitors with back side power rails | Jiann-Tyng Tzeng | 2025-06-10 |
| 12315861 | Integrated circuit structure and method for manufacturing the same | Wei Ling Chang, Lee-Chung Lu, Xiangdong Chen, Hsiang-Chi Huang | 2025-05-27 |
| 12278230 | Method of manufacturing conductors for semiconductor device | Chih-Liang Chen, Hui-Ting Yang, Shun Li Chen, Ko-Bin Kao, Chih-Ming Lai +2 more | 2025-04-15 |
| 12261113 | Middle-end-of-line strap for standard cell | Meng-Hung Shen, Chih-Liang Chen, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Wei-Cheng Lin | 2025-03-25 |
| 12261115 | Semiconductor devices and methods of manufacturing thereof | Jiann-Tyng Tzeng | 2025-03-25 |
| 12255203 | Monolithic three dimensional integrated circuit | Jiann-Tyng Tzeng, Shih-Wei Peng | 2025-03-18 |
| 12230624 | Integrated circuit with mixed row heights | Jiann-Tyng Tzeng, Chung-Hsing Wang, Yi-Kan Cheng | 2025-02-18 |
| 12219748 | Semiconductor device including a dielectric layer between a source/drain region and a substrate | Yi-Hsun Chiu | 2025-02-04 |
| 12218050 | Manufacturing method for semiconductor device | Te-Hsin Chiu, Wei-An Lai, Meng-Hung Shen, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2025-02-04 |