Issued Patents 2025
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12368078 | Dual-side power rail design and method of making same | Chih-Chao Chou, Shang-Wen Chang, Ching-Wei Tsai, Chih-Hao Wang | 2025-07-22 |
| 12363879 | FinFET SRAM cells with reduced fin pitch | Chih-Hao Wang, Yi-Hsiung Lin, Shang-Wen Chang | 2025-07-15 |
| 12347748 | Semiconductor device and method of manufacturing the same | Yi-Bo Liao, Chun-Yuan Chen, Lin-Yu Huang, Chih-Hao Wang | 2025-07-01 |
| 12327765 | Semiconductor device with contact structures | Yi-Hsiung Lin, Shang-Wen Chang | 2025-06-10 |
| 12272605 | Methods of forming contact features in field-effect transistors | Yi-Hsiung Lin, Shang-Wen Chang | 2025-04-08 |
| 12260897 | Separated read BL scheme in 3T dram for read speed improvement | Hidehiro Fujiwara, Yih Wang | 2025-03-25 |
| 12243781 | Semiconductor device with L-shape conductive feature and methods of forming the same | Cheng-Chi Chuang, Li-Zhen Yu, Yu-Ming Lin, Chih-Hao Wang | 2025-03-04 |
| 12234145 | Methods for wafer bonding | Chien-Wei Chang, Ya-Jen Sheuh, Ren-Dou Lee, Yi-Chih Chang, Yuan-Hsin Chi | 2025-02-25 |
| 12237233 | Backside power rail for physical failure analysis (PFA) | Chih-Chao Chou, Shang-Wen Chang, Ching-Wei Tsai, Chih-Hao Wang | 2025-02-25 |
| 12230572 | Backside signal interconnection | Yu-Xuan Huang, Ching-Wei Tsai, Yi-Bo Liao, Kuan-Lun Cheng, Wei-Cheng Lin +6 more | 2025-02-18 |
| 12218047 | Memory devices and methods of manufacturing thereof | Meng-Sheng Chang, Chia-En Huang, Yih Wang | 2025-02-04 |
| 12219748 | Semiconductor device including a dielectric layer between a source/drain region and a substrate | Kam-Tou Sio | 2025-02-04 |
| 12193204 | Memory devices and methods of manufacturing thereof | Meng-Sheng Chang, Chia-En Huang, Yih Wang | 2025-01-07 |