Issued Patents 2025
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12388013 | Three dimensional integrated circuit with monolithic inter-tier vias (MIV) | Shih-Wei Peng, Jiann-Tyng Tzeng, Kam-Tou Sio, Wei-Cheng Lin | 2025-08-12 |
| 12388016 | Deep lines and shallow lines in signal conducting paths | Te-Hsin Chiu, Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng, Chia-Tien Wu | 2025-08-12 |
| 12307183 | Variable width nano-sheet field-effect transistor cell structure | Wei-Cheng Lin, Yan-Hao Chen, Jiann-Tyng Tzeng, Lipen Yuan, Hui-Zhong Zhuang +1 more | 2025-05-20 |
| 12288785 | Layout designs of integrated circuits having backside routing tracks | Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng | 2025-04-29 |
| 12230572 | Backside signal interconnection | Yu-Xuan Huang, Ching-Wei Tsai, Yi-Hsun Chiu, Yi-Bo Liao, Kuan-Lun Cheng +6 more | 2025-02-18 |
| 12218050 | Manufacturing method for semiconductor device | Te-Hsin Chiu, Meng-Hung Shen, Wei-Cheng Lin, Jiann-Tyng Tzeng, Kam-Tou Sio | 2025-02-04 |
| 12218057 | Integrated circuit with backside interconnections and method of making same | Shih-Wei Peng, Te-Hsin Chiu, Ching-Wei Tsai, Jiann-Tyng Tzeng | 2025-02-04 |
| 12218141 | Hybrid fin field-effect transistor cell structures and related methods | Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Wei-Cheng Lin, Lipen Yuan, Yan-Hao Chen | 2025-02-04 |
| 12204838 | Structure and method for tying off dummy gate in semiconductor device | Jiann-Tyng Tzeng, Shih-Wei Peng, Meng-Hung Shen | 2025-01-21 |