| 12405787 |
Utilizing structured sparsity in systolic arrays |
Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Chandra Gurram, Chunhui Mei +10 more |
2025-09-02 |
| 12399685 |
Systolic array having support for output sparsity |
Jorge Parra, Fangwen Fu, Subramaniam Maiyuran, Varghese George, Mike B. Macpherson +6 more |
2025-08-26 |
| 12386617 |
Gathering payload from arbitrary registers for send messages in a graphics environment |
Chandra Gurram, Fan-Yin Tzeng, Subramaniam Maiyuran, Guei-Yuan Lueh, Timothy Bauer +2 more |
2025-08-12 |
| 12375262 |
Fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) workloads in a graphics environment |
Wajdi K. Feghali, Changwon Rhee, Wei-Yu Chen, Timothy Bauer, Alexander Lyashevsky |
2025-07-29 |
| 12346694 |
Register file for systolic array |
Chandra Gurram, Wei-Yu Chen, Fangwen Fu, Sabareesh Ganapathy, Varghese George +4 more |
2025-07-01 |
| 12242846 |
Supporting 8-bit floating point format operands in a computing architecture |
Naveen Mellempudi, Subramaniam Maiyuran, Varghese George, Fangwen Fu, Shuai Mu +1 more |
2025-03-04 |
| 12236238 |
Large integer multiplication enhancements for graphics environment |
Li-An Tang, Changwon Rhee, Timothy Bauer, Alexander Lyashevsky, Jiasheng Chen |
2025-02-25 |
| 12210905 |
Multiple register allocation sizes for threads |
Chandra Gurram, Wei-Yu Chen, Vikranth Vemulapalli, Subramaniam Maiyuran, Jorge Eduardo Parra Osorio +2 more |
2025-01-28 |
| 12190158 |
Using sparsity metadata to reduce systolic array power consumption |
Jorge Parra, Jiasheng Chen, Chandra Gurram |
2025-01-07 |
| 12189571 |
Dual pipeline parallel systolic array |
Jorge Parra, Jiasheng Chen, Fangwen Fu, Sabareesh Ganapathy, Chandra Gurram +2 more |
2025-01-07 |