Issued Patents 2025
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12423102 | Instructions to convert from FP16 to BF8 | Alexander Heinecke, Robert Valentine, Mark J. Charney, Christopher J. Hughes, Evangelos Georganas +3 more | 2025-09-23 |
| 12417100 | Instructions for structured-sparse tile matrix FMA | Menachem Adelman, Amit Gradstein, Alexander Heinecke, Christopher J. Hughes, Shahar Mizrahi +7 more | 2025-09-16 |
| 12412232 | Dynamic precision management for integer deep learning primitives | Dheevatsa Mudigere, Dipankar Das, Srinivas Sridharan | 2025-09-09 |
| 12405787 | Utilizing structured sparsity in systolic arrays | Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Chandra Gurram, Chunhui Mei +10 more | 2025-09-02 |
| 12399685 | Systolic array having support for output sparsity | Jorge Parra, Fangwen Fu, Subramaniam Maiyuran, Varghese George, Mike B. Macpherson +6 more | 2025-08-26 |
| 12367045 | Instructions to convert from FP16 to BF8 | Alexander Heinecke, Robert Valentine, Mark J. Charney, Christopher J. Hughes, Evangelos Georganas +3 more | 2025-07-22 |
| 12314727 | Optimized compute hardware for machine learning operations | Dipankar Das, Roger Gramunt, Mikhail Smelyanskiy, Jesus Corbal, Dheevatsa Mudigere +1 more | 2025-05-27 |
| 12288062 | Instructions for fused multiply-add operations with variable precision input operands | Dipankar Das, Mrinmay Dutta, Arun Kumar, Dheevatsa Mudigere, Abhisek KUNDU | 2025-04-29 |
| 12242846 | Supporting 8-bit floating point format operands in a computing architecture | Subramaniam Maiyuran, Varghese George, Fangwen Fu, Shuai Mu, Supratim Pal +1 more | 2025-03-04 |
| 12198055 | Incremental precision networks using residual inference and fine-grain quantization | Abhisek KUNDU, Dheevatsa Mudigere, Dipankar Das | 2025-01-14 |