Issued Patents 2025
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12405787 | Utilizing structured sparsity in systolic arrays | Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Chunhui Mei, Durgesh Borkar +10 more | 2025-09-02 |
| 12399685 | Systolic array having support for output sparsity | Jorge Parra, Fangwen Fu, Subramaniam Maiyuran, Varghese George, Mike B. Macpherson +6 more | 2025-08-26 |
| 12386617 | Gathering payload from arbitrary registers for send messages in a graphics environment | Supratim Pal, Fan-Yin Tzeng, Subramaniam Maiyuran, Guei-Yuan Lueh, Timothy Bauer +2 more | 2025-08-12 |
| 12346694 | Register file for systolic array | Wei-Yu Chen, Fangwen Fu, Sabareesh Ganapathy, Varghese George, Guei-Yuan Lueh +4 more | 2025-07-01 |
| 12333306 | High performance constant cache and constant access mechanisms | Subramaniam Maiyuran, Sudarshanram Shetty, Travis T. Schluessler, Guei-Yuan Lueh, PingHang Cheung +3 more | 2025-06-17 |
| 12210905 | Multiple register allocation sizes for threads | Wei-Yu Chen, Vikranth Vemulapalli, Subramaniam Maiyuran, Jorge Eduardo Parra Osorio, Shuai Mu +2 more | 2025-01-28 |
| 12189571 | Dual pipeline parallel systolic array | Jorge Parra, Jiasheng Chen, Supratim Pal, Fangwen Fu, Sabareesh Ganapathy +2 more | 2025-01-07 |
| 12190158 | Using sparsity metadata to reduce systolic array power consumption | Jorge Parra, Supratim Pal, Jiasheng Chen | 2025-01-07 |