Issued Patents 2025
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12399685 | Systolic array having support for output sparsity | Jorge Parra, Subramaniam Maiyuran, Varghese George, Mike B. Macpherson, Supratim Pal +6 more | 2025-08-26 |
| 12346694 | Register file for systolic array | Chandra Gurram, Wei-Yu Chen, Sabareesh Ganapathy, Varghese George, Guei-Yuan Lueh +4 more | 2025-07-01 |
| 12242846 | Supporting 8-bit floating point format operands in a computing architecture | Naveen Mellempudi, Subramaniam Maiyuran, Varghese George, Shuai Mu, Supratim Pal +1 more | 2025-03-04 |
| 12198222 | Architecture for block sparse operations on a systolic array | Abhishek R. Appu, Subramaniam Maiyuran, Mike B. Macpherson, Jiasheng Chen, Varghese George +3 more | 2025-01-14 |
| 12189571 | Dual pipeline parallel systolic array | Jorge Parra, Jiasheng Chen, Supratim Pal, Sabareesh Ganapathy, Chandra Gurram +2 more | 2025-01-07 |