Issued Patents 2024
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12068377 | Back-end-of-line devices | Yu-Hsiang Chen, Po-Hsiang Huang, Wen-Sheh Huang, Hsing-Leo Tsai | 2024-08-20 |
| 12068023 | Memory circuits, memory structures, and methods for fabricating a memory device | Chieh Lee, Yi-Ching Liu, Wen-Chang Cheng, Jonathan Tsung-Yung Chang | 2024-08-20 |
| 12063773 | Layout structure including anti-fuse cell | Meng-Sheng Chang, Wan-Hsueh Cheng, Yao-Jen Yang, Yih Wang | 2024-08-13 |
| 12063786 | Compute-in-memory device and method | Chieh Lee, Yi-Ching Liu, Wen-Chang Cheng, Yih Wang | 2024-08-13 |
| 12062408 | Switches to reduce routing rails of memory system | Meng-Sheng Chang, Yi-Ching Liu, Yih Wang | 2024-08-13 |
| 12058868 | Semiconductor memory devices with arrays of vias and methods of manufacturing thereof | Meng-Han Lin | 2024-08-06 |
| 12052859 | Non-volatile memory device with reduced area | Meng-Sheng Chang, Yao-Jen Yang, Yih Wang | 2024-07-30 |
| 12051464 | Semiconductor memory devices with different word lines | Meng-Sheng Chang, Gu-Huan Li | 2024-07-30 |
| 12048147 | Layout structure including anti-fuse cell | Meng-Sheng Chang, Wan-Hsueh Cheng, Yao-Jen Yang, Yih Wang | 2024-07-23 |
| 12029042 | 3D memory device with modulated doped channel | Peng-Chun Liou, Zhiqiang Wu, Chung-Wei Wu, Yi-Ching Liu | 2024-07-02 |
| 12027204 | Memory including metal rails with balanced loading | Meng-Sheng Chang, Yi-Ching Liu, Yih Wang | 2024-07-02 |
| 12020996 | Systems and methods of testing memory devices | Meng-Han Lin | 2024-06-25 |
| 12014768 | DRAM computation circuit and method | Chieh Lee, Yi-Ching Liu, Wen-Chang Cheng, Yih Wang | 2024-06-18 |
| 12010833 | Method and structure for reduce OTP cell area and leakage | Meng-Sheng Chang, Shao-Yu Chou, Yih Wang | 2024-06-11 |
| 12002528 | Memory device and operating method of the same | Gu-Huan Li, Tung-Cheng Chang, Perng-Fei Yuh, Chun-Ying Lee, Yih Wang | 2024-06-04 |
| 12002499 | Using split word lines and switches for reducing capacitive loading on a memory system | Sheng-Chen Wang, Meng-Han Lin, Yi-Ching Liu | 2024-06-04 |
| 11996409 | Stacking CMOS structure | Yu-Xuan Huang, Ching-Wei Tsai, Kuan-Lun Cheng | 2024-05-28 |
| 11997843 | 4CPP SRAM cell and array | Hidehiro Fujiwara, Yen-Huei Chen, Yih Wang | 2024-05-28 |
| 11996140 | SRAM structure with asymmetric interconnection | Yi-Hsun Chiu | 2024-05-28 |
| 11985819 | Layout method by buried rail for centralized anti-fuse read current | Meng-Sheng Chang | 2024-05-14 |
| 11984165 | Memory device with reduced area | Chun-Ying Lee, Chieh Lee | 2024-05-14 |
| 11978509 | Semiconductor memory devices with differential threshold voltages | Meng-Sheng Chang, Yih Wang | 2024-05-07 |
| 11980035 | Three-dimensional memory devices and methods of manufacturing thereof | Meng-Han Lin | 2024-05-07 |
| 11963348 | Integrated circuit read only memory (ROM) structure | Geng-Cing Lin, Ze-Sian Lu, Meng-Sheng Chang, Jung-Ping Yang, Yen-Huei Chen | 2024-04-16 |
| 11955201 | Memory device | Meng-Sheng Chang, Yi-Ching Liu, Yih Wang | 2024-04-09 |